Somewhat OT - falling behind the times ...

what kind of tv is that?

It is a Loewe Xelos A26 - basically a high end flat panel unit. Being German, it comes with a circuit diagram.

Dave

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And a URL to download the fill for the PROM?

Tom

Strange that - you'd have thought if you're making TV's you'd plan to sell enough to pay for an ASIC

Could be a time-to-market thing :) Sell lots, then go to asic later.

Jeremy

Or even better (from Xilinx' perspective), reinvest the income from being early to market into your next generation of product, rather than spending the big bucks recreating in ASIC something that's already working and selling.

John

Or a Digital TV effect. I see the FCC is trying to mandate obsolescence on all Analog TVs in the USA, by forcing a move to digital.

Waste / landfill ? Not our problem!!

This is a high stakes gamble: would you roll an ASIC, or use an FPGA while you wait to see the what the political fallout and lobbying brings, once the dust settles ?

-jg

Actually these TVs are generally based on atleast one ASIC (a video decoder and scaler), and an FPGA. The FPGA generally has some simple glue logic, sitting between the ASIC and the LCD panel. LCD panels from different manufacturers, many of which are available in mechanically compatible form factors, often have different electrical and timing characteristics. With the LCD panel the single largest cost item in a TV, leaving the glue logic programmable allows the manufacturers to treat the panel as a commodity item. I would not expect this FPGA "socket" to go away any time soon.

Regards, Erik.

Hi Jeremy,

You're absolutely right. TV makers make a new TV asic every, let's say, three years, in order to minimize NRE cost.

New features are being implemented in FPGA _and_ incorporated in the next-generation ASIC. After three years, you'll have an FPGA-less TV, with one _with_ FPGA (with new features) coming out the year after, etc etc.

Also, I've written LCD driver code for [TV maker] so that they could be flexible with panel timing and signalling, thereby freeing them from panel maker lock-in, and start designing for panels whose specs weren't quite finished yet.

Best regards,

Ben