Latest threads in Field-Programmable Gate Arrays

Update on availability of Spartan3

I want to update my post on the availability of Spartan3. I called NuHorizons and was able to get a quote on XC3S200-4P...

1 21yrs

barrinst

1 21yrs barrinst

area group constraint for quadranting

hi all, sorry to be a bit vague chaps, but where is the information about modular design - in particular the appnote/ma...

1 21yrs

not

1 21yrs not

Lean Ethernet on Digilent board?

Has anyone used the Ethernet add-on module for the Digilent Spartan3 board? http://www.digilentinc.com/info/NET1.cfm I...

0 21yrs

iluvfpgas

0 21yrs iluvfpgas

Xilinx FFT

Hello, I am trying to connect a FFT module generated with coregen to a microprocessor. The problem is that the micropro...

0 21yrs

jcastillo

0 21yrs jcastillo

Re: Idea exploration - Image stabilization by means of software.

>> >>Are you taking pictures of stationary things from a stationary camera? That's >>what the astronomy case involves....

2 21yrs

jonathan.bromley

2 21yrs jonathan.bromley

Xlinix configuration: DONE pin too early?

Hello, We use different Xilinx FPGAs (Spartan3, Virtex2, etc.). When downloading the code, everything works fine except...

13 21yrs

guenter.wolpert

13 21yrs guenter.wolpert

Error :device requires cache coherent memory for BD's

Hi All, EDK6.2 sp2 generated VxWorks comes up with following warning when the cache is enabled.OPB_Ethernet is used. ema...

0 21yrs

ivan.fed

0 21yrs ivan.fed

Free Xilinx Cable III for owners of Altera MAX2 Starterkit.

Hi due to the fact that Xilinx EDK 7.1 Debugger does not support Xilinx platform USB cable and Virtex 4 I was forced to...

0 21yrs

antti

0 21yrs antti

comp.arch.fpga.<mfr>

I see a lot of posts here that are specific to a single vendor's devices or that device-vendor's tools. I think it woul...

11 21yrs

megacz

11 21yrs megacz

IPIF LogiCore?

Hi there, I'm trying to build a new core that will use a IPIF PLB interface to connect to the PLB. Most of my logic is...

1 21yrs

mdales

1 21yrs mdales

Atmel tools: any way to edit intra-cell connections in IDS/Figaro?

Hey, is there any way to alter stuff *inside* a cell (like the LUT table or muxes) using Figaro/IDS? It's really cool t...

0 21yrs

falkjack

0 21yrs falkjack

PCI in a PCI-X slot

I have a implemented a PCI 66Mhz master/target design on an Fpga, using an IP core from one of the well known suppliers...

1 21yrs

amyler

1 21yrs amyler

AbusivepPricing information in marketing publications

Xilinx is doing it again. http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=s3e_overview "Spartan-3E FPGA device...

9 21yrs

news

9 21yrs news

question about xilinx micro kernel

in its edk (embedded system development kit), xilinx provide a micro kernel for the microblaze/ppc405 core in some type...

0 21yrs

chongpeng

0 21yrs chongpeng

Need application note for Motion controller with Xilinx

Hello sir This is Seoul Korea. I'm Mr. Lee. The reason that I'm writing letter is regarding for Application note for Mo...

1 21yrs

engtech1

1 21yrs engtech1

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