Hi, can we disconnect the power suppy to some Macrocells which are not using in the design or functionality for a perticular time or all the time, So that I can save the overall power consumption Is there any arrangement is available in the CPLD to cut off the power supply for unused Macrocells by using clock gating.
Please Answer this.
Regards, Hima.
In Xilinx CoolRunner CPLDs the current consumed by each unused macrocell is already a small fraction of a microamp. Not worth any extra hoopla. Peter Alfke
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...
The OP said he want to power down some macrocells for some time and to do clock gating to reduce power. I dont think he referes to macrocells that are not used at all (which as you said draw almost no power since the are automatically disabled by the software).
Clock gating is no problem, but do it properly(tm). Power down, controled by logic at runtime inside the CPLD is not possible.
Regards Falk
O.K., so let me be more specific: There is no way to physically detach anything inside the CoolRunner from Vcc, but it's also not necessary. Static current consumption is close to zero. As long as you prevent nodes from wiggling, they consume practically no power. "Proper" clock gating is one way, but not the only way. One can also gate the logic in front of the flip-flop (which really is what Clock Enable does anyhow). Peter Alfke
Not quite.
There are different CPLD cores :
a) Those that use Wide AND sense amplifiers, with FLASH Logic fuses, have high currents ( tens of mA) and they can save power by power-down. Altera and Atmel have a PD pin, and Atmel's L models also have edge-transition shutdown - they wake up/sense logic/clock MC/sleep again. Their static Icc is some uA
b) Those that have CMOS trees and load the steering/fuse logic, at power up. These have no run time FLASH read currents, and are faster, but do have a finite startup time. [and possible RAM corruption issues ? ] The Coolrunner CPLDs are in this family, as are the new Lattice 4000, and the MAX II. Static Iccs in these are in the some uA region.
All CPLDs have clock enables, but that saves only the Q power, and not the Clock Tree drive power.
So the answer to the OP, varies with the core-model. Individual run-time MC Power control is not available to the user, but device wide and automatic/inherent power control, is in there already.
-jg
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