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circuit optimization - a feedbackless machine

Lets consider an abstract machine generating a new word from in a finite space at every its step in a deterministic way. We have a golden word (a key). The goal is to get its index in the sequence of the words. That is, once the generator has produced the key word, the machine stops and the word counter keeps the resulting index.

The implementation of the design involves a "clock enable" MUX at each FF. That is, the running generator will load next state on every clk while stopped FSM will persist it state. The MUXes in this architure will be controlled by the feedback signal

done = (current_word = golden_key)

Well, my question is about "clocked enable" efficiency in the ordinary FPGAs. I am considering a design avoiding the feedback in order to maximize generator's speed (and reduce hardware demands). We could start the generator by pushing its reset input. Once the generator produces the anticipated word at its output at some moment of time, we would latch the index (result of computation) letting the machine rush further. We are not interested in the machine anymore, we have obtained the result and can let it blow up. How advantageous would be this 2nd design?

Reply to
valentin tihomirov
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Valentin, what is your question? Clock Enable is very efficient in FPGAs. Being "free" must be the ultimate efficiency :-) Xilinx FPGAs always have a CE input that does not interfere with other logic, and is a synchronous input (really a multiplexer that makes the flip-flop either look at the new data, or at its own Q.) Peter Alfke, Xilinx Applications (from home)

Reply to
Peter Alfke

Valentin, what is your question? Clock Enable is very efficient in FPGAs. Being "free" must be the ultimate efficiency :-) Xilinx FPGAs always have a CE input that does not interfere with other logic, and is a synchronous input (really a multiplexer that makes the flip-flop either look at the new data, or at its own Q.) Peter Alfke, Xilinx Applications (from home)

Reply to
Peter Alfke

OK, as muxes are already there we would better exploit em. Do the FPGAs comprise the prerouted CE signal trace? In fact, I have make some synthesis experementation and the controlled solution space explorer compromizes only about 1% of the "free" implementation speed. That's curious.

-- controlled elsif Rising_Edge then if not DONE then STATE

Reply to
valentin tihomirov

Dear Valentin,

It depends on whether the synthesized logic is FF with asynchronous reset or not, as using SRL stuff can give some advantages as well. It also depends on how many states are in your the state machine, and its implementation. If you are going to use one-hot encoding, then "clock enable"-less design is likely to run faster, otherwise it may not. If you could give more details...

Hope this helps

Vladislav

Reply to
Vladislav Muravin

Valentin, an FPGA is a fixed structure where many (but not all) connections can be programmed. The CE multiplexer is fixed, you cannot eliminate or bypass it. You can only decide to use it, or leave it permanently connecting the input directly to the flip-flop's D input. Therefore, I do not undestand your question. Peter Alfke, Xilinx

Reply to
Peter Alfke

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