Just gloating

I've got a VHDL design in which I use record types as a convenient way of wiring up my internal buses. This design is a single-master, multiple slave bus. The default assignment to all of the slaves puts don't cares ('X', actually) on the data and address lines for any slave not currently in use, it's only the control signals that get specific assignments that tell the slave it's not in use.

You'd think that, in this case, the optimized logic for the slave data and address buses would simply be a wire. Today I built the design under Quartus 12.0. And that was exactly what happened. My don't cares were actually handled in a logical manner that reduced the amount of logic used.

The last time I tried this, under ISE 12.3, this was not the case, and I wasted a huge amount of effort getting the excess logic out of my data and address paths so as to keep from using up unnecessary resources and complicating my timing. Today, what should have just worked just worked.

It's a good day.

Rob Gaddi, Highland Technology -- www.highlandtechnology.com
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Rob Gaddi
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Am 25.09.12 02:32, schrieb Rob Gaddi:


Maybe you used an not so actual architecture last time (like Spartan 3)? Xilinx did improvements on xst, but only for the newer chip families. But you can try "-use_new_parser yes" on xst.

See the solutio section:

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regards, Bart

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Bart Fox

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