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Multiple IDELAYCTRLs in V-5: how, and why?

I'm on Virtex-5, and have a lot of IODELAYs, for fixed and variable input delays. I've read chapter 7 of the User Guide, and AR #39966, about IODELAY_GROUPs. I need to instantiate one or more IDELAYCTRLs, and my options are (1) to instantiatiate one of them, and let the tool fix everything up, or (2) instantiate lots of them, and do it all by hand.

Here's the bit I don't understand. What's wrong with (1)?

Page 342 of ug190 says "The most efficient way to use the IDELAYCTRL module is to define and lock down the placement of every IDELAYCTRL instance used in a design....Xilinx strongly recommends using IDELAYCTRL with a LOC constraint", but the UG doesn't seem to say anywhere why this is the case. What's the point? And why don't the tools just conenct up the IDELAYCTRLs anyway, without being told to? The IODELAY is useless without it.

Thanks.

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nospam
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The IDELAYCTRL is one of the most poorly handled structures in the V5. That being said, I believe the user guide was written before the introduction of the IODELAY_GROUP to the tools. Using groups is the new "preferred" method. In a simple system where you have only one 200MHz reference clock and don't use the LOCK output of the IDELAYCTRL, you can either use the original option (1) - one IDELAYCTRL and no LOC constraint - or you can assign all IODELAYs to the same IODELAY_GROUP. If you're unfortunate enough to work on an XPS / EDK design, then you might need to have multiple IODELAY_GROUP constraints to avoid hand placement of all IDELAYCTRL's.

-- Gabor

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Gabor

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