Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

XILINX DCMs and synthesis results

I have been wondering about how to use DCMs in a design lets say im doing some dsp filter design and I want my embedded...
2 comments posted 21yrs
posted by wallge
2 comments posted 21yrs posted by wallge

Cyclone Dev. Board, how to set lower clk freq?

I am using Altera's Cyclone EPIC20F4007 Development board and nios I processor The problem is that I am unable to set t...
0 comments posted 21yrs
posted by jmakias
0 comments posted 21yrs posted by jmakias

iMPACT downloading error

Hello, I'm a graduate student working with Xilinx ML310 board. I have general question about using iMPACT. When I tried...
1 comments posted 21yrs
posted by bhkim91
1 comments posted 21yrs posted by bhkim91

nios2 gnu sources broken for amd64 linux

Hello Does somebody know who is responsible for the GNU sources of the NIOS2 toolchain? Since nothing was ever put back...
2 comments posted 21yrs
posted by me
2 comments posted 21yrs posted by me

NIOS2 subscription online?

Wasn't there once on Altera's website the possibility to extend the NIOS2 subscription? Any reason it was removed? thx r...
1 comments posted 21yrs
posted by me
1 comments posted 21yrs posted by me

How about signed adder?

Hi all, I want to add two 6 bits signed digit. Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' is...
3 comments posted 21yrs
posted by zhushenli
3 comments posted 21yrs posted by zhushenli

Chipscope problem

Hello Guys, I am facing some problem in using chipscope. I am using chipscope core inserter has i synthesis my code usi...
0 comments posted 21yrs
posted by stud_lang_jap
0 comments posted 21yrs posted by stud_lang_jap

FPGA :FFT Core in Xilinx

Hi Any body used FFT core given by coregenerator in Xilinx ? Does it work as they said in their data sheet.. regards bij...
4 comments posted 21yrs
posted by pbijoy
4 comments posted 21yrs posted by pbijoy

Virtex-4 FX devices availablity issues

Hi, has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX bigger than the FX12? And I'm talking about seei...
1 comments posted 21yrs
posted by smd
1 comments posted 21yrs posted by smd

DC Offset removal in FPGA

Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can re...
4 comments posted 21yrs
posted by shridhar
4 comments posted 21yrs posted by shridhar

Xilinx Powe Requirements V2PRO complaint

I'm designing with a V2PRO and its config PROM. I noticed that I will need: 1. VCCint (PROM) = 1.8V 2. VCCint (FPGA) =...
3 comments posted 21yrs
posted by robnstef
3 comments posted 21yrs posted by robnstef