Latest threads in Field-Programmable Gate Arrays

Issues with Xilinx xapp635: Interface for TigerSharc Link Ports.

Hello, Started to look at the xapp635 to implement link port interface in Virtex II device. I ran a simulation (VHDL ve...

6 21yrs

brijesh_xyz

6 21yrs brijesh_xyz

XILINX DCMs and synthesis results

I have been wondering about how to use DCMs in a design lets say im doing some dsp filter design and I want my embedded...

2 21yrs

wallge

2 21yrs wallge

Cyclone Dev. Board, how to set lower clk freq?

I am using Altera's Cyclone EPIC20F4007 Development board and nios I processor The problem is that I am unable to set t...

0 21yrs

jmakias

0 21yrs jmakias

iMPACT downloading error

Hello, I'm a graduate student working with Xilinx ML310 board. I have general question about using iMPACT. When I tried...

1 21yrs

bhkim91

1 21yrs bhkim91

nios2 gnu sources broken for amd64 linux

Hello Does somebody know who is responsible for the GNU sources of the NIOS2 toolchain? Since nothing was ever put back...

2 21yrs

me

2 21yrs me

NIOS2 subscription online?

Wasn't there once on Altera's website the possibility to extend the NIOS2 subscription? Any reason it was removed? thx r...

1 21yrs

me

1 21yrs me

ANN: Project VeriPage Announces New Articles on SystemVerilog, PSL

Project VeriPage announces three new articles this month. As always, these and all other articles on Project VeriPage a...

0 21yrs

mittra

0 21yrs mittra

How about signed adder?

Hi all, I want to add two 6 bits signed digit. Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' is...

3 21yrs

zhushenli

3 21yrs zhushenli

Xilinx Impact-Tool: Error when downloading partial bitstream

Hello! Impact fails, if I want to download a partial bitstream after a normal working fully bitstream has been download...

0 21yrs

markusjung1

0 21yrs markusjung1

using GUI and batch mode produces different results !

Hello all, I am having a strange thing happening. This was not urgent, so i kinda did not post it previously... I have...

4 21yrs

muravinv

4 21yrs muravinv

Chipscope problem

Hello Guys, I am facing some problem in using chipscope. I am using chipscope core inserter has i synthesis my code usi...

0 21yrs

stud_lang_jap

0 21yrs stud_lang_jap

FPGA :FFT Core in Xilinx

Hi Any body used FFT core given by coregenerator in Xilinx ? Does it work as they said in their data sheet.. regards bij...

4 21yrs

pbijoy

4 21yrs pbijoy

Minimum allowed clock frequency for Nios 2 processor (Stratix 2)

Hi, I wanted to know if there is any lower limit on the minimum possible clock frequency that can be given to a Nios 2...

10 21yrs

shiladitya.biswas

10 21yrs shiladitya.biswas

Virtex-4 FX devices availablity issues

Hi, has anyone ever seen a Virtex-4 FX-part with RocketIO-MGTs? Any FX bigger than the FX12? And I'm talking about seei...

1 21yrs

smd

1 21yrs smd

DC Offset removal in FPGA

Hi, we are reading an ADC o/p through FPGA. To remove the DC Offset present in the ADC input we have a DAC which can re...

4 21yrs

shridhar

4 21yrs shridhar

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays