Latest threads in Field-Programmable Gate Arrays

IP-cores for digital audio

Hello experts! I have to implement a receiver for AES/EBU digital audio to I2S-Bus on a Xilinx Spartan3 FPGA. Concernin...

2 21yrs

usenet0705

2 21yrs usenet0705

Optimizing out a divide on altera cyclone fpga

Ok, hi all, I'm new to fpgas and am having some fun with an Altera UP3 kit. In the app I'm developing I have a componen...

7 21yrs

sfernald

7 21yrs sfernald

Creating Variable Delay for output signals in an XCV1000

Hello, I am interfacing a XCV1000 to an old MIPS R3000. I am generating a 50 MHz clock using a DLL with an input clock...

4 21yrs

johnd

4 21yrs johnd

FPGA + DIMM SDRAM

Hello, I want to connect a DIMM SDRam to a Cyclone FPGA, but I don't really feel confortable about the way of doing it....

0 21yrs

nick

0 21yrs nick

All of the design is being optimized away and logic removed

I using the Xilixn tool flow. After synthesis with XST, the synthesis report looks fine, it contains all the Flip flops...

7 21yrs

azamirfan

7 21yrs azamirfan

Design is too large for the device! xc3s400

Hi, I am currently working with the 1727 bit wide shift register....For my design requirements, I had to change it to a...

29 21yrs

gmethi

29 21yrs gmethi

Generics of type time and XST synthesis

I'm new to FPGA synthesis and XST, so I could use some help. I'm synthesizing an entity for the first time, and I'm rec...

1 21yrs

killerhertz

1 21yrs killerhertz

DDR SDRAM configuration

Hi, I have programmed my FPGA with an evaluation bitstream file for DDR-SDRAM controller. When measuring bank address b...

0 21yrs

ALuPin

0 21yrs ALuPin

Using unregistered inputs in FSM

Hi, I have some doubts concerning the following problems: In my design I have an 8bit bidiretional bus "Data_ulpi". Whe...

25 21yrs

ALuPin

25 21yrs ALuPin

General-purpose STAPL Composer?

I'm working with FPGA's that use STAPL bitstreams. In addition to the standard configuration bitstream, I'd also like t...

5 21yrs

ad.rast.7

5 21yrs ad.rast.7

Virtex-4 hot-swappable?

I saw the appnote that pertains to older devices and the Answers Database had a reference to it being in the V4 PCB Desi...

4 21yrs

JDDesignAndConsulting

4 21yrs JDDesignAndConsulting

Ones Count 64 bit on Xilinx in VHDL

Hello Group, What is the best way to count 64 incoming simultaneous bit signals to determine the number of 1s (in VHDL)...

22 21yrs

bradsmallridge

22 21yrs bradsmallridge

Xilinx sysace + xmd -jprog options.

We have multiple Xilinx FPGAs on our jtag chain. The main VP20 ppc is loaded first. It detects what other cards/FPGA pl...

1 21yrs

tony.p.lee

1 21yrs tony.p.lee

ChipScope Pro : how to set up trigger

Hi I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3. As an exercise, I want to insert 'logic analyzer(ILA...

5 21yrs

pasacco

5 21yrs pasacco

Xilinx equivalent of simplify constrains.

Dear friends i am now converting synplify project to the Xilinx environment. I need help on the constrain conversion fr...

2 21yrs

vssumesh_asic

2 21yrs vssumesh_asic

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