Field-Programmable Gate Arrays

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Heat Sink for Stratix

Hi, Is there anybody who have utilized a heat sink for stratix FPGA I need a thermal resistance less than 6°C/W because...
0 comments posted 21yrs
posted by patrick.melet
0 comments posted 21yrs posted by patrick.melet

IP-cores for digital audio

Hello experts! I have to implement a receiver for AES/EBU digital audio to I2S-Bus on a Xilinx Spartan3 FPGA. Concernin...
2 comments posted 21yrs
posted by usenet0705
2 comments posted 21yrs posted by usenet0705

Optimizing out a divide on altera cyclone fpga

Ok, hi all, I'm new to fpgas and am having some fun with an Altera UP3 kit. In the app I'm developing I have a componen...
7 comments posted 21yrs
posted by sfernald
7 comments posted 21yrs posted by sfernald

FPGA + DIMM SDRAM

Hello, I want to connect a DIMM SDRam to a Cyclone FPGA, but I don't really feel confortable about the way of doing it....
0 comments posted 21yrs
posted by nick
0 comments posted 21yrs posted by nick

Design is too large for the device! xc3s400

Hi, I am currently working with the 1727 bit wide shift register....For my design requirements, I had to change it to a...
29 comments posted 21yrs
posted by gmethi
29 comments posted 21yrs posted by gmethi

Generics of type time and XST synthesis

I'm new to FPGA synthesis and XST, so I could use some help. I'm synthesizing an entity for the first time, and I'm rec...
1 comments posted 21yrs
posted by killerhertz
1 comments posted 21yrs posted by killerhertz

DDR SDRAM configuration

Hi, I have programmed my FPGA with an evaluation bitstream file for DDR-SDRAM controller. When measuring bank address b...
0 comments posted 21yrs
posted by ALuPin
0 comments posted 21yrs posted by ALuPin

Using unregistered inputs in FSM

Hi, I have some doubts concerning the following problems: In my design I have an 8bit bidiretional bus "Data_ulpi". Whe...
25 comments posted 21yrs
posted by ALuPin
25 comments posted 21yrs posted by ALuPin

General-purpose STAPL Composer?

I'm working with FPGA's that use STAPL bitstreams. In addition to the standard configuration bitstream, I'd also like t...
5 comments posted 21yrs
posted by ad.rast.7
5 comments posted 21yrs posted by ad.rast.7

Virtex-4 hot-swappable?

I saw the appnote that pertains to older devices and the Answers Database had a reference to it being in the V4 PCB Desi...
4 comments posted 21yrs
posted by JDDesignAndConsulting
4 comments posted 21yrs posted by JDDesignAndConsulting

Ones Count 64 bit on Xilinx in VHDL

Hello Group, What is the best way to count 64 incoming simultaneous bit signals to determine the number of 1s (in VHDL)...
22 comments posted 21yrs
posted by bradsmallridge
22 comments posted 21yrs posted by bradsmallridge

Xilinx sysace + xmd -jprog options.

We have multiple Xilinx FPGAs on our jtag chain. The main VP20 ppc is loaded first. It detects what other cards/FPGA pl...
1 comments posted 21yrs
posted by tony.p.lee
1 comments posted 21yrs posted by tony.p.lee

ChipScope Pro : how to set up trigger

Hi I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3. As an exercise, I want to insert 'logic analyzer(ILA...
5 comments posted 21yrs
posted by pasacco
5 comments posted 21yrs posted by pasacco