IP-cores for digital audio

Hello experts!

I have to implement a receiver for AES/EBU digital audio to I2S-Bus on a Xilinx Spartan3 FPGA. Concerning my level of FPGA-knowledge, I'm through the basic and in-depth tutorials from Xilinx and the whole flashing-LED and stopwatch-stuff ;-) and have also implemented designs of this level on my own. But there's no experience in larger, more complex designs.

During my search I came across the SPDIF Interface and I2S Cores from opencores.org, which seem to be way too high for understanding for me at the moment. Has anyone successfully implemented them on a FPGA and could give me a rough idea of the necessary knowledge and engineering effort?

The other possibility would be using a commercial IP-core, like for example from coreworks.pt. I've already established contact, their offer seems quite promising. But for comparison reasons, does anybody know other providers for digital audio interface IP-cores?

Any help will be greatly appreciated! Holger

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Holger Blum
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Holger Blum wrote in news:dbo09c$acv$ snipped-for-privacy@online.de:

Altera has an application note for theier devices:

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Al Clark
Danville Signal Processing, Inc.
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Al Clark

I designed an SPDIF to I2S audio disembedder about 2 years ago for a client. It's pretty straightforward, like a couple of days max. should see it done ok once you're up to speed on what you need. The one I did was for an Altera Stratix but the only family specific bit was a fifo.


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