I have to implement a receiver for AES/EBU digital audio to I2S-Bus on a Xilinx Spartan3 FPGA. Concerning my level of FPGA-knowledge, I'm through the basic and in-depth tutorials from Xilinx and the whole flashing-LED and stopwatch-stuff ;-) and have also implemented designs of this level on my own. But there's no experience in larger, more complex designs.
During my search I came across the SPDIF Interface and I2S Cores from opencores.org, which seem to be way too high for understanding for me at the moment. Has anyone successfully implemented them on a FPGA and could give me a rough idea of the necessary knowledge and engineering effort?
The other possibility would be using a commercial IP-core, like for example from coreworks.pt. I've already established contact, their offer seems quite promising. But for comparison reasons, does anybody know other providers for digital audio interface IP-cores?
Any help will be greatly appreciated! Holger