Virtex-4 hot-swappable?

JD,

V4 is just like V2, V2P, V2P-X, and S3: it has traditional CMOS output structures that have the diodes to ground and Vcco as part of the nfet and pfet devices themselves.

"hot swap" means many different things to many people -

1. The most strict: insertion and removal of a device from a parallel bus must not affect data being sent/received by others on the bus. This is really tough. Even if the diodes aren't there (such as in a competitor's part) there is still the power on/off of the IO and its intrinsic capacitive loading (however small). At slow speeds this works if the diodes are not present, but at high speeds the secondary factors become primary, and even the "hot swap" part that claims full compliance fails to meet the requirement of no glitches whatsoever.

1. Less strict: insertion and removal which uses a stepped or sequenced connector. This is achievable. Our app notes detail these solutions. They apply to V4 equally as to V2 or V2P. By sequencing the connections, one can overcome the diode issue of clamping, and the potential glitching issue by control of the pins prior to their mating. Again, some engineering is required, but it does work.

2. Common: insertion and removal on a parallel bus that uses a protocol to recognize insertion, and back off and retry (or ignor). Nice, because you do nothing, and the system is designed to work even if there are glitches.

1. Self-powering: since the diode to Vcco can be forward biased, and the IO bank in the V4 needs 8 mA to power ON completely, the IO bank can be powered from the wide parallel bus itself. A number of customers figured this out (with our help), and their system backplanes work this way. No glitches as the bus uses a very strong driver on transmitting cards (which all together end up powering ON the IO banks of inserted cards without glitching -- they are guaranteed to power on tri-state before configuration).

2. MGT's, LVDS, or other point to point: here "hotswap" just means that no damage is done when you insert/remove. And, no damage is done to the MGTs on V2, V2P, or V4. Data isn't the issue (when the board is unplugged, there is no point to point link!).

Hope this helps,

Austin

Austin,

I appreciate all of the detail, but I guess my concern was more simple:

1. Will I damage my V4 devices if the I/O pins get driven when the core is unpowered?
2. Are there current paths from the I/O pins to the supply that could cause the device to get "powered" from driving the I/O with the core unpowered?

Apologies for using the term "hot-swap" if it is not the correct one :)

Thanks,

JD

Austin,

Any help appreciated.

Thanks,

JD

JD,

1. No you will not damage the FPGA with the core unpowered. However, remember that there are intrinsic diodes from IO pins to Vcco, and to ground. So if you connect Vcco to ground, and then connect all the IOs to another operating chip, you will have a diode to ground forward biased on every IO pin, probably blowing out the driving device, unless it is tough enough to handle it, Often the FPGA is accused of damaging the driver, as the FGPA will tolerate up to 200 mA sink or source for weeks without damage (same as shorting one of our pins to ground or Vcco, and leaving it there).

1. If the Vcco is just coming from a regulator or power supply, 99.99% of all such supplies are open, until powered. Thus the diodes will power ON the Vcco. That is harmless. The IOs power ON tristate, and then wait for the core and aux supplies to come up before configuring. Before, during, and immediately after configuring, all IO is tristate. Right up until DONE goes high, and then your design decides what to do with the IOs (they can stay tristate until your design sees a command on a bus, etc.).

Austin