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Generics of type time and XST synthesis

I'm new to FPGA synthesis and XST, so I could use some help.

I'm synthesizing an entity for the first time, and I'm receiving warnings and errors related to the time type in my models. I realize that they are not synthesizable. I'm okay with the warnings because I have them in there for functional simulation only.

Here is the output from XST in Foundation 7.1:

WARNING:Xst:828 - "/../../../../work/toplevel.vhd" line 28: Constant of type Time is ignored. WARNING:Xst:1537 - "/../../../../work/toplevel.vhd" line 93: Generic of type Time is ignored.

Analyzing generic Entity (Architecture ). ERROR:Xst:834 - "/../../../../work/component_g.vhd" line 58: Generic has not been given a value.

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It seems to me like XST is ignoring the time types and then later
complaining about a generic of type time in the component
instantiation, the value of which, is propogated from a higher level.
Any thoughts?
Reply to
Brandon
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It's sorta weird that the top-level entity is being synthesized before the lower level entity.

Also, according to page 295 of the XST User Guide v7.1i, "Generic parameters may be declared in the entity declaration part. XST supports all types for generics including integer, boolean, string, real, std_logic_vector, etc." but then, on page 314 under the heading "VHDL Language Support," we're told that in the entity header, Generics are supported for integers only, and further down, under "Physical Types," we're told that TIME is ignored.

You may be best off using "synthesis translate_off" and "synthesis translate_on" pragmas around the generics you don't want XST to see.

-a

Reply to
Andy Peters

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