Hello,
I want to implemented a gated clock signal that is active for only a certain period. What is the best way?
I did it like this (I know that is bad)
wire clock_coding; assign clock_coding = (counter > 5 && counter < 120)?clock:1'b0;
Thanks,
then don't (if you know is bad) leave the clock to run and use CE (chip enable) driven by your counter to mask the unwanted clock cycles Aurash
-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
This isn't necessarily bad. It's O.K. to gate clocks when they are slow enough to avoid setup or hold issues. The code you wrote would work O.K. if counter increments on negedge clock so you won't glitch when the count changes.
In ASIC's you can save power by gating clocks, but in an FPGA you're probably better off using a clock enable, because the clock global routing is already there and flip-flops all come with enable inputs whether you use them or not.
Regards, Gabor
If you don't know how to code using clock enables, try something like:
wire enable; assign enable = (counter > 5 && counter < 120);
always @(posedge clk) if (reset) begin // do reset stuff in here end else if (enable) begin // do real work in here end
Hope this helps.
John Providenza
If you're clocking everything with a single clock edge, hold time violations are not a function of clock speed; there is no "slow enough."
Bob Perlman Cambrian Design Works
You may use a block buffer (Virtex-II family) with enable, which provides glitch-free operation. If you may use this signal as a clock enable for other clock, this would also be a nice alternative.
Vladislav
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