You can easily accomplish the digital requirements in an FPGA. The problem comes with the analog.
You either need 1) a 24:1 analog mux or 2) 24 channels of slope circuitry and comparator. I would NOT recommend using the FPGA inputs as precision comparators.
Multichannel A/D converters are available off-the-shelf but 24 channels may be hard to accommodate in fewer than 3 devices at a cost you would like. Check out Analog Devices at analog.com or some of you other "favorite" analog houses.
20 mV for 1 LSbit for 8 bits at 5V may be workable but are the inputs happy with 5V swing? The slope method I recall cahrged a cap up from 0V from a voltage-controlled current source for a fixed time and back down to 0V from a fixed constant-current source. The count gave the A/D value. The 0V could be moved to a nice Vref level. The charge-up voltage could be large and resistor-limited to the FPGA so the out-of-range high voltage (limited by the I/O protection diode) always gives a good high result and the finish/end crossover is well within the specified ranges. The problem still remains: 24 channels of analog MUX or 24 channels of slope circuitry.
FPGA usually do not contain comparator inputs which you need for a slope conversion. How about using a cheap ADC plus a few low cost 8:1 muxes (74HC or CD series)?
Silicon Labs have small uC that can do 32 Channel ADC, in 12 bit or 8 bit : they are 2.5V Max IP, so you'll need 2:1 dividers.
Any FPGA solution will not be very pin or external component efficent. The FPGA can easily do the PWM / Counter side of any ADC, but you need external divider, signal conditioning, and integration.
Most vanilla is a R-C-R charge balancing system,[needs 48 pins] but that would struggle to give 8 bits, and be prone to FPGA supply noise.
Adding external analog SW will improve PSRR, and an external comparitor would improve precision, but you can see on 24 channels, you are quickly past a single chip uC.....
When Xilinx patents an application on our FPGAs (ie a use patent), one can use it with OUR FPGAs, without restriction. However, we are not likely to license it for free for use with a competitor's product.
If you need a letter to that effect, please contact our legal dept.
That would be an option. However, I was thinking about a mux that is around 10dB lower in cost. Three CD4051 should do which run about $0.15 to $0.18 a pop in >1k quantities. The HC versions must somehow have fallen from grace because they are sometimes unavailable and when you find them they are expensive. Guess the market didn't accept them much.
The Xilinx lvds differential inputs are actually pretty good comparators but I doubt you could get a solid 8 bits from them. Besides, single-slope adc's are tacky.
I bet you could do a good delta-sigma adc in an fpga, with a few external parts.
But the op needs a cheap 8-bit adc and a mux. There's nothing very complex about multiplexing.
Some more info, so you don't think I'm completely crazy :).
First, I made a big mistake in my original post and said 2 milliseconds instead of 2 *micro* seconds. My target sample latency is under 2 microseconds.
Currently, I am multiplexing all inputs down into a 8-input ADC that feeds a uC. I have a latency of 8 us per sample (microseconds, not ms as I originally said) and samples are obtained round-robin. I want to reduce the latency down to 1 us if possible, and also grab all samples at once.
I have trouble finding an 8-input+ ADC, 8-bit resolution+, 1 Msamples/sec that doesn't cost an arm and a leg.
A new design I am working on will need an FPGA anyway, so I wanted to suck the ADC+uC functionality into the FPGA (probably Xilinx) if possible.
Could a delta-sigma style ADC be able to produce new samples at 1 us (1Msamples/sec) w/8-bit+ resolution? I can live with the multiplexing since I'm having to do that anyway.
I am guessing the external circuitry would be a comparator, RC network for filtering the PWM, and maybe a FET/BJT to clear the cap of charge?
I have done a lot of tacky tricks in electronics. Other things they said in design reviews were "weird, gross, unorthodox, yech, ...". Somehow that always happens when cost rules.
I am not sure what these diff inputs would do on slow transitions. If they'd let off a wee oscillation-like burst every time the FCC might not be so enthused about that.
Or just use a really cheap audio converter, maybe the kind that is in the $4.99 sound cards. Heck, you even get more bits, like buy eight and get another eight for free.
Thanks to the CD4051 it would boil down to about two cents per channel. Just my two cents :-)
Do you know what happened to the HC4051? They became expensive and non-stock in a lot of places. Did they fall from grace?
We would never think that way of anyone. Well, most of us wouldn't.
Oops, three orders of magnitude. That calls for a "real" ADC. I am not sure whether it would make sense to do that within an FPGA but John would be the expert on that, not me. Just keep in mind that your FPGA size and thus cost might grow beyond of what a simple ADC would have cost and you can't really mux with them.
Sound like a good concept. I don't think there is a decently price ADC with 24 inputs.
How about TLV1570? 8-channel 10bits for well under $4.
ADS7888 is a serial 8-bit one-channel for under a buck. Can't beat that, really. For muxing the CD4051 is a bit hard pressed at 1usec but can possibly be used.
You will have trouble competing on cost and performance with e.g., LTC2236, 10-bit 25 MS/s for $4.67 in singles. All you need to add is an external 8:1 multiplexer like a MAX4312 ($4.45).
That ADC part has a 6-cycle latency, at 25 MS/s that's only 240 ns. You could stop it down to 8 MS/s (to lower power dissipation) and still hit your 1 us latency and throughput goals. Depends on what clocks you have available.
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