Lattice iCECube2 for iCE40 Devices

It's been a while since I used any Lattice tools, but I seem to remember that Synplify for Lattice has a compiler directive that encourages it to use a particular signal as a clock enable. In your case you could apply this to RateEn and see if it causes the synthesizer to recognize it as an enable to reduce the LUT count. That being said, I have not used the ICE series parts and there may still be another reason why the tools have not inferred clock enables.

-- Gabor

I thought the tile in an iCE40 was not as smart as the MachXO2, and so that was why any iCE40 design uses more cells ? Did you try re-targeting to the MachXO2 ?

-jg

Thanks for the reply. You might be right. A simple divide by two FF also uses the logic to implement an enable. I'll look into the directive. Seems rather retarded really. Most of the time the synthesizer will even add logic to the enable and with these tools it doesn't want to use the enable at all.

I'll give the directive a try.

I did put in a ticket for this and we'll see what they say. The iCE40 parts started out with their own tools so it's hard to say what might have happened when they were brought over to Lattice.

Rick

was why any iCE40 design uses more cells ?

I looked at the documentation and the only restriction I could see is that all the clock enables within a block share the same input pin. So there is only one clock enable for the entire block. I wouldn't think this is a real problem, at least not one that required using extra LUTs. Even if you are using the extra input, each LUT has four and there are only four inputs, counter value, carry in, up/down flag and enable. Also, the extra LUT is combining the up/down flag and the enable flag. Why would that have to be done more than once? So this is messed up in three different ways...

We'll see what Lattice says.

Rick