Latest threads in Field-Programmable Gate Arrays

USB power and debug signals on micro USB connector

For a handheld device, powered by a Li-ion cell, I need a charge power input. Most standard chips for charging and powe...

3 13yrs

stef33d

3 13yrs stef33d

FPGA DSP basics: clock enable / new clock

My current goal is to implement some digital signal processing (filters) on a FPGA. I am currently using Terasics DE0 n...

7 13yrs

me

7 13yrs me

DC fifo behaviour at underflow/overflow

We all know that a fifo should operate without getting empty or full. Does anybody have experience of what sort of outp...

21 13yrs

3619

21 13yrs 3619

MII SFD Detection with Shematics

Hello, I have to detect the Start of a Ethernet Frame. So I want to make use of a FPGA. The FPGA will be connected to t...

8 13yrs

bln5320

8 13yrs bln5320

Where to move for an embedded software engineer.

I assume the bay area is number one for embedded software engineers, but where else are the big markets, as companies r...

18 13yrs

notaclue

18 13yrs notaclue

Is this Multicycle?

Assume register r4 is driven by three registers r1, r2, r3 registers r1, r2, r3 drive out their data every 3 clocks, ea...

5 13yrs

3619

5 13yrs 3619

Looking for evaluators for NEW Vector Processor for FPGAs, offers massive parallel performance, all programmable in C/C++

We are looking for testers/evaluators of our newly released MXP Matrix proc essor for Altera FPGAs (Xilinx very soon)....

2 13yrs

reisses

2 13yrs reisses

How to transfer multiple bit data between phase shifted clock?

Hi All, I am designing a memory controller and I am using two clocks clk and clk_90. Phase difference between clk and c...

4 13yrs

3940

4 13yrs 3940

USB Cable - RHEL 6.2 and ISE 13.3

Hello. I'm having trouble using the "Platform Cable USB II" with my new linux box. Basically, when I plug the USB cable...

1 13yrs

1845

1 13yrs 1845

V6 BUFR -> BUFG clocking structure (hold issue?)

Hi! I have a Xilinx webcase for about 2mo about this that goes nowhere ... may be better luck here. My problem: - V6 de...

28 13yrs

iiahim

28 13yrs iiahim

VHDL expert puzzle

In the following link, a design is presented that alledgedly has a flaw. The claim is that this is a simple case and th...

72 13yrs

jan

72 13yrs jan

Set-up and hold times and metastability

Hi, I've been looking at synchronising data across clock domains, and have managed to confuse myself. Can someone confi...

24 13yrs

3681

24 13yrs 3681

Spartan 3A startup

So, after being assured Spartan 3A should be around for a while (Thanks, all who commented) I made a board for a Sparta...

4 13yrs

elson

4 13yrs elson

A total beginner, wondering about determining hardware specs. requirements

Hi, I'm just starting to learn Verilog/systemverilog and I've been running some of my code through simulators to ensure...

2 13yrs

ivantolk

2 13yrs ivantolk

question about verilog ?, :

Hi, I know some VHDL, but totally new to verilog. Now I am reading a verilog template. I do not know the meaning of the...

6 13yrs

rxjwg98

6 13yrs rxjwg98