TTA-based Co-design Environment (TCE) is a toolset for designing application-specific processors based on the Transport Triggered Architecture (TTA). The toolset provides a complete retargetable co-design flow from high-level language programs down to synthesizable processor RTL (VHDL and Verilog backends supported) and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
This release adds support for LLVM 3.2, initial support for half-precision floats, improved vector support and OpenCL host-tta-device mode simulation with pocl's ttasim driver. See the CHANGES file for a more thorough change listing.
Acknowledgements
---------------- Many thanks to Dr. Erno Salminen for his improvements on the TCE User Manual, and to Antti Hayrrinen for his first code contributions to this release. Keep them coming!
We'd like to thank the Radio Implementation Research Team of Nokia Research Center and Academy of Finland (funding decision 253087) for financially supporting most of the work for developing this release. Much appreciated!
Links
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TCE home page: