Hi All Is it possible to send test vectors through Chipscope to the FPGA via JTAG and then get outputs to verify the functionality of the desgin configured? Can anyone please explain? Anuja
- posted
18 years ago
Hi All Is it possible to send test vectors through Chipscope to the FPGA via JTAG and then get outputs to verify the functionality of the desgin configured? Can anyone please explain? Anuja
pulse train can be sent using vio but it is limited to length of 16. I think it is because of SRLs being use in vio? any one any idea?
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