Hi, we do not succeed in compiling our design using mixed voltage I/O macros in ACTEL Designer 6.2 (SP2). To illustrate the problem, we have reduced it to a simple 2-input AND gate . (If someone wants to try we have attached the VHDL and the edif files below.) The error message is : Error: A mixed-voltage I/O macro is found in the design. This macro type is not supported. When Vddp = 2.5V, use XX25LPXX macro. When Vddp = 3.3V, use XX33XX I/O macro.
Please contact Actel Technical Support at 1-800-262-1060 or snipped-for-privacy@actel.com for more information.
According to the documentation, application notes and knowledge base on the ACTEL website, we were lead to believe that the device apa-150 powered with VDDp=3.3V is able to drive or receive both 2.5 and 3.3V compatible signals (except for the 25LP macros). Has anyone encountered this problem or know how to solve it ?
regards, J . Buytaert CERN, Geneva
VHDL:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use work.apa_comps.all;
entity test1 is port( in1,in2 : in std_logic; out1 :out std_logic ); end;
architecture arch of test1 is component ib25S port( Y : out std_logic; PAD : in std_logic ); end component; component ob33PH port( A : in std_logic; PAD : out std_logic ); end component; signal in1b, in2b, out1b : std_logic;
begin out1b