Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

gast division carry chain usage

This excellent website discusses fast division: http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/DiviRa.htm I was...
0 comments posted 20yrs
posted by brannonking
0 comments posted 20yrs posted by brannonking

Anyone used the Xilinx' floating point core?

Hi there, has anyone used Xilinx' floating point core with a Virtex2 Pro? I get the same strange error in ISE the whole...
2 comments posted 20yrs
posted by sheinzle
2 comments posted 20yrs posted by sheinzle

Carry Chain Design

The carry chains in current Xilinx FPGAs are insufficient for comparison logic. I propose some changes for future chip...
5 comments posted 20yrs
posted by brannonking
5 comments posted 20yrs posted by brannonking

Simple PWM Spartan 3

i need help for a Simple PWM Spartan 3, i dont know how to activat the spartan3 board hel
3 comments posted 20yrs
posted by fecs
3 comments posted 20yrs posted by fecs

Newbie question: XC3S400 Gate Count

Hi, I am a FPGA newbie. Here's my question: How do you count the gates in Xilinx FPGA? I have a XC3S400 board, which is...
9 comments posted 20yrs
posted by jerryzy
9 comments posted 20yrs posted by jerryzy

Program FPGA from PowerPC in V2P

Hi, I'm working with the Virtex-II Pro FPGA. Is there a way that we can run VHDL code for FPGA in PowerPC405 cores? So...
3 comments posted 20yrs
posted by dasani8888
3 comments posted 20yrs posted by dasani8888

clock timing

Hi, I am driving a LCD display with a pixel clock of 66 MHz. The pixels are stored in a fifo, for parallel to lvds conv...
15 comments posted 20yrs
posted by benjamin
15 comments posted 20yrs posted by benjamin

FPGA timming

Does anyone know of a good reference for timing concepts in synchronous FPGA designs. I know what false and multi-cycle...
9 comments posted 20yrs
posted by kunal.shenoy
9 comments posted 20yrs posted by kunal.shenoy

Data2Mem usage - help required

THIS IS IN CONTINUATION TO THE THREAD I MADE A COUPLE OF DAYS AGO. I WANTED TO ISOLATE THIS FROM THE OTHER STUFF, HENCE...
5 comments posted 20yrs
posted by robertsolanki
5 comments posted 20yrs posted by robertsolanki

Rosetta Results

All, http://tinyurl.com/clzqh Details the latest readouts for actual single event upsets for Virtex 4, and Spartan 3. T...
9 comments posted 20yrs
posted by austin
9 comments posted 20yrs posted by austin

using i2c core

hi, im trying to use i2c open source core available from opensorces.org and having problems with cofiguring the "scl" a...
18 comments posted 20yrs
posted by manusha
18 comments posted 20yrs posted by manusha

XChecker cable and chipscope

Is there a way to use chipscope with a card which works with an old XChecker cable?
1 comments posted 20yrs
posted by taileb.mehdi
1 comments posted 20yrs posted by taileb.mehdi

chipscope pro problem

hi, im using chipscope pro core inserter to prepare my design for analysis. in my project i have two top level entities...
0 comments posted 20yrs
posted by manusha
0 comments posted 20yrs posted by manusha

LSI RAPIDCHIP

Greetings, I posted this in comp.cad.synthesis. That group doesn't have much traffic. We are looking into doing a rapid...
6 comments posted 20yrs
posted by nospam
6 comments posted 20yrs posted by nospam