1. Home
  2. Field-Programmable Gate Arrays
  3. Carry Chain Design

Carry Chain Design

The carry chains in current Xilinx FPGAs are insufficient for comparison logic. I propose some changes for future chip designs:

First, if this can be done on a Stratix 2 carry chain, please state how.

We are going to do a LT or GT comparison. The plan for LT:

chop the thing into 2 bit chunks for the most significant chunk: if (a < b) switch the chain high if (a > b) switch the chain low if (a == b) passthrough repeat for next most significant chunk tie the bottom of the chain low

So you see the problem? I can't force the chain high or low at run time and still allow for passthrough. I can only do one or the other.

Reply to
Brannon
Loading thread data ...

Carry chain compares are done all the time. They work great. Your definition is how they're implemented If your single bit "a" and single bit "b" are considered: if( ab ) force b (which is low) onto the chain if( a==b ) pass the carry in to carry out. A comparison is just a subtraction.

Reply to
John_H

You have a good point. I should have clarified. The subtraction only uses two inputs per LUT. The same is the case with what you're proposing for the compare. It seems to me you could double the density by adding an extra switch bit to the MUXCY because the LUT already supports four inputs.

Reply to
Brannon

Might be good for compare, but since the LUT still has only one output you couldn't build an adder/subtracter, for which the carry chain was optimized.

Reply to
Gabor

So to clarify: You want 2 bits of "a" and 2 bits of "b" to drive the 16-entry LUT for the carry chain select AND you want an 8-entry LUT for the Direct Input of the carry chain mux?

Reply to
John_H

I guess what I was picturing was a four bit LUT (like it currently is in Xilinx chips) with two outputs where one output was tied to an AND gate on the output of the MUXCY. Or that extra bit could be tied to the select bits on the MUXCY and the MUXCY could have three or four inputs, two of which could be from CY0. Currently only one input on the MUXCY is from CY0, and there is only one CY0 per MUXCY. That looks like a cheap, small part to me. We should be able to easily add another one, and possibly tie it to the upper bits going into the LUT.

Reply to
Brannon

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.