Field-Programmable Gate Arrays

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LSI RAPIDCHIP

Greetings, I posted this in comp.cad.synthesis. That group doesn't have much traffic. We are looking into doing a rapid...
6 comments posted 21yrs
posted by nospam
6 comments posted 21yrs posted by nospam

Error (XST): translate terminal to FCT

Dear During synthesizing in XST of ISE 6.3, following error (?) is encountered.... Does anyone have experience on this...
1 comments posted 21yrs
posted by pasacco
1 comments posted 21yrs posted by pasacco

Low-cost, high-quality design team

If you are looking for a low-cost, high-quality design team, take a look at Crystal Instruments (website: www.go-ci.com...
0 comments posted 21yrs
posted by digitalsignal999
0 comments posted 21yrs posted by digitalsignal999

Implementing I2C master

HEllo everybody, I'm interested in the implementation of a master I2C controller on a FPGA. I found some implementation...
1 comments posted 21yrs
posted by giovanniparodi79
1 comments posted 21yrs posted by giovanniparodi79

About with Synplify Pro?

Hello everybody!When I use synplify Pro to synthesis,it tells me: @E:Internal Error Why?How to solve it?Thanks!
0 comments posted 21yrs
posted by seabrench
0 comments posted 21yrs posted by seabrench

Mixed voltage in JTAG chain.

Hi all, Is it ok to have mixed voltage in the JTAG chain? (say 2.5V and 3.3V). It seems to be ok from the documentation...
2 comments posted 21yrs
posted by subhasri.krishnan
2 comments posted 21yrs posted by subhasri.krishnan

3.3v<->5V

Hi all, I am new to logic design in general, but I am getting an FPGA development board (the Spartan-3 board from xilin...
7 comments posted 21yrs
posted by alt.spam
7 comments posted 21yrs posted by alt.spam

Implementing five stage pipeline

Hi all, Thinking of a 5 stage pipeline risc. 1. fetch 2. decode 3. execute 4. buffer 5. write back The result of execut...
13 comments posted 21yrs
posted by vssumesh_asic
13 comments posted 21yrs posted by vssumesh_asic

Problem with Xilinx Impact under windowsXP

I am using a FPGA kit, when I download the bitstream, under windowsXP operating system, I get an error "Done did not go...
1 comments posted 21yrs
posted by rakesh
1 comments posted 21yrs posted by rakesh

CPLD design software under WINE?

Have You got any experiences running design software for windowses under WINE & Linux or plain Linux for X86 or other L...
6 comments posted 21yrs
posted by mika.leinonen
6 comments posted 21yrs posted by mika.leinonen

xilinx fpga beginner question

Hello, I am a beginner with fpgas with practically no experience with this material, working as an undergraduate resear...
1 comments posted 21yrs
posted by eyeh
1 comments posted 21yrs posted by eyeh

Synplify Pro and automatic Retiming/Pipelining

Hi everybody! Synplify Pro offers Retiming, which allows register relocation across combinatorial logic. However, this...
2 comments posted 21yrs
posted by sheinzle
2 comments posted 21yrs posted by sheinzle

Help me

Who can give me(A fresh man) some advice about the FPGA learning,and how to become an expert in it.Please recommend some...
2 comments posted 21yrs
posted by zqhpnp
2 comments posted 21yrs posted by zqhpnp

FPGA : PCI core needed

Hi My company wanted to buy PCI core(33Mhz), and it should be fitted in spartan-3 fpga and should not take not more tha...
2 comments posted 21yrs
posted by pbijoy
2 comments posted 21yrs posted by pbijoy

Linux and Platform USB Cable

Has anyone gotten impact to work on Linux with the Platform USB Cable?? If so, what version of the kernel were you usin...
1 comments posted 21yrs
posted by chris
1 comments posted 21yrs posted by chris