Xilinx Package/Logic Options

"Eli Hughes" schrieb im Newsbeitrag news:dknncg$1ik2$ snipped-for-privacy@f04n12.cac.psu.edu...

possible the FPGA vendors see no interest in that. pitty.

I would really welcome some FPGA in QFN40, with onchip USB and etherner PHY :)

but the FPGAs in small packages are rather small. The best small is possible s3e-500 in CP132 8b8 mm

for ceramic packages i bet the times are over forever.

Antti

BGA packages are FAR easier to deal with in automated reflow for a number of reasons. BGAs are also the smallest footprint/connection technology around, which is important to a lot of people. Another thread was noting that to get high levels of logic usually entails getting a lot of pins as well.

I understand the desire for non-BGA versions (There's been a number of times I wished for it), but the commercial market probably won't sustain it in very high pin count packages.

Cheers

PeteS

What are military/space people using these days? (I thought that was the reason for ceramic packages in the old days.)

-- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.

The last space project I was on (earlier this year) was to use a Virtex2 in a ceramic column grid array. It's basically a ceramic BGA with solder columns instead of balls. I believe the reasoning behind the columns is that they will allow more differential thermal expansion before the stress pops the part off the board. It is still a ceramic package, but not in a form factor that is any easier for a hobbyist to use than a bga package, and it is a heck of a lot more expensive.