Latest threads in Field-Programmable Gate Arrays

SDRAM controller.

Hi Guys, I am writing a SDRAM controller (for the first time), its a Micron MT48LC16M16 sdram. I am having a little tro...

3 20yrs

bohr_singh

3 20yrs bohr_singh

Is this even true???

Hey all, I am designing(trying to design) an sdram controller (for a PC133 module) to work as fast as it is possible an...

7 20yrs

subhasri.krishnan

7 20yrs subhasri.krishnan

Signal timing problem

I am having difficulty solving a timing problem using a Spartan 3 embedded platform. We are using a MicroBlaze core wit...

6 20yrs

tlassiter

6 20yrs tlassiter

Can't pack into OLOGIC

Hi, It's a few days since I can't put a FF into IOB register: XST (7.1.4) option: -equivalent register removal: NO -pac...

10 20yrs

john.wo.71

10 20yrs john.wo.71

open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm

has anyone in the dig. design and reconfig. computing community looked seriously at open source hardware design librari...

49 20yrs

wallge

49 20yrs wallge

fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors

I was looking for some documentation on recent speed and logic density enhancements on modern fpgas (i have searched xi...

7 20yrs

wallge

7 20yrs wallge

Looking for tutorials for bootloader writing on xilinx SOC ??

Hi, We are using EDK 6.3 on PPC and Microblaze designs. I will have to write bootloaders for loading firmwares and OS f...

3 20yrs

t

3 20yrs t

Coolrunner output pins stuck at 0V

Maybe someone can make a suggestion: I'm building a board with a Coolrunner XPLA3384 on it, however, my intitial (very...

5 20yrs

johannes.vanderhorst

5 20yrs johannes.vanderhorst

Spartan 3e is slower than Virtex 2p

Since Spartan 3e is a generation later and 90nm instead of 130nm, I expected it to be faster than Virtex 2p. But it is...

2 20yrs

alan

2 20yrs alan

In Xilinx, how do I delay a signal by a fraction of a clock cycle?

I am outputting a data with a clock 12.5MHz, which will latch the data into external chip whose input delay is unknown....

10 20yrs

Francis.invalid

10 20yrs Francis.invalid

Rocket IO reset problem

Hello, I currently work on Rocket IO in vertex II pro with eval board. I succeed loopback test in parallel mode, but wh...

1 20yrs

jdonjdon

1 20yrs jdonjdon

Xilinx Block RAM - initializing with Intel Hex-File

Hello, how can I initialize a 8k*8 Block RAM with an Intel Hex-File? Thanks for any hint. Udo

1 20yrs

WeikEngOff

1 20yrs WeikEngOff

Best Case Timing Parameters

Hi All, If any of you folks know how, to calculate the best case timing parameters for a Xilinx FPGA (for eg: Global cl...

7 20yrs

ajay

7 20yrs ajay

How do i detect ethernet frames of layer 2 using ethereal?

Hello everyone, I am trying to implement ethernet MAC on a fpga using vhdl. I have a transmit module which generates th...

4 20yrs

achiluka

4 20yrs achiluka

Multilinx, where do I get 3.3V power?

I am using MultiLinx to program my XC2V1000 thru JTAG connector. I got TMS, TCK, TDI, TDO correctly, but unable to find...

1 20yrs

FrancisChee

1 20yrs FrancisChee

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