Xilinx routing details

Is there a description of some type on Xilinx' routing resources within its FPGA's? I am currently using a Spartan3 but will probably be using a Virtex on future projects. Are the gory details proprietary info? Specifically, I would like to know how the switching matrix works. And the long lines/short lines...when to use...how they are used...etc.

Thanks.

Reply to
motty
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fpga editor is an interesting tool to explore the internal resources of each family.

Reply to
Totally_Lost

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