Dear all,
I have the following ALU code as part of a data path:
-- purpose: simple ALU -- type : combinational -- inputs : a, b, op_sel -- outputs: y alu : PROCESS (a, b, op_sel) BEGIN -- PROCESS alu CASE op_sel IS WHEN "0000" => -- increment y -- decrement y -- test for zero y -- addition y -- subtract, compare y -- logical and y -- logical or y -- logical xor y -- logical not y -- shift left logical y -- shift right logical y y
This is a functional description, to get the correct logical output. it goes into the synthesis program and gets massively reduced. For instance, the separate increment/decrement logic will get folded into one adder logic with a few extra gates to perform the two functions. So, the resulting logic actually implemented in an FPGA will not resemble what you describe at all, but will be pretty well optimized for the specific chip architecture.
Jon
1 - I only see 12 items in the case, where did 14 come from?
2 - What synthesis tool are you using & what part are you targetting? A lot of optimization is architecture-specific. If your part is good at implementing wide muxes, maybe the solution your synthesis tool found is a good one. If it were me using Xilinx tools, I'd look at the worst case delays after map (route delays not included) to see how many levels of logic they have and how fast they go. Note that some "logic levels" (e.g. LUT) cause more delay than others (e.g. carry chain).
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