Field-Programmable Gate Arrays

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Parallella-16 lowest-cost xilinx zynq kit

The crowdfunded Parallella-16 starter kit from adapteva seems to be the lowest-cost xilinx zynq starter kit at the same...
0 comments posted 13yrs
posted by acd4usenet
0 comments posted 13yrs posted by acd4usenet

NiosII 8.0 make error Windows XP

I am trying to build a simple hello world example using Nios II v8.0 on a w indows Xp machine. I see the following erro...
5 comments posted 13yrs
posted by vivek.menon79
5 comments posted 13yrs posted by vivek.menon79

seperate high speed rules for HDL?

Hi everyone. I'm trying to find out if, at high speeds, it is necessary to clock every other register using every other...
15 comments posted 13yrs
posted by sketyro
15 comments posted 13yrs posted by sketyro

Instruction time (lwi) on Microblaze

Hi, I'm trying to accomodate with microblaze on a spartan starter kit 3a board and now I'm looking into measuring execu...
0 comments posted 13yrs
posted by 98245
0 comments posted 13yrs posted by 98245

vtr and at40k

Hello, Has anybody ever attempted to craft a libarchfpga architecture file for the at40k FPGAs? As I understand it, ver...
0 comments posted 13yrs
posted by klammerj
0 comments posted 13yrs posted by klammerj

serial protocol specs and verification

Hi all, I have the following specs for the physical level of a serial protocol: > For the communication with Frontend a...
41 comments posted 13yrs
posted by alessandro.basili
41 comments posted 13yrs posted by alessandro.basili

New Relay Computer

I've made a new relay computer: check out http://relaysbc.sourceforge.net (look for the videos on the example programs...
0 comments posted 13yrs
posted by jhallen
0 comments posted 13yrs posted by jhallen

FF Replication with Xilinx ISE

Hi, I have a design that needs to stall a long pipeline (with the CE input of registers). The module receiving data fro...
4 comments posted 13yrs
posted by capossio.leonardo
4 comments posted 13yrs posted by capossio.leonardo

Nios II problem with DDR core SOPC builder

Hello all: I am currently transitioning a Quartus 8.0 (subscription edition) project to Quartus 12.1 (web edition). I a...
6 comments posted 13yrs
posted by vivek.menon79
6 comments posted 13yrs posted by vivek.menon79

Verilog: "don't care" in

Hi, is there any simple way to point out impossible cases in comparison operators? For example, I have the expression re...
3 comments posted 13yrs
posted by 24789
3 comments posted 13yrs posted by 24789

Xilinx ISE GUI vs tcl script problem

Hello I've used tcl scripts for quite a long time now and been very happy until yesterday when suddenly the script inte...
2 comments posted 13yrs
posted by nmatringe
2 comments posted 13yrs posted by nmatringe

Metastability mitigation and I/O registers

This is a design targetted at a Microsemi ProASIC3 device, but I expect that the answer should be technology-independen...
14 comments posted 13yrs
posted by 2161
14 comments posted 13yrs posted by 2161

Floorplanning Literature

Any good floorplanning literature (papers, books, etc.) ? I'm needing it for floorplanning FPGA architectures (Spartan...
6 comments posted 13yrs
posted by capossio.leonardo
6 comments posted 13yrs posted by capossio.leonardo