Hello All,
It has been many years since I used the Synopsys Design Constraint (SDC) la nguage to apply timing constraints to a logic design. Right now I am worki ng on a preexisting Altera Cyclone 4 FPGA design and I believe that the I/O constraints are not complete. Unfortunately, my first attempts to constra in I/O on the part result in Altera timing reports that are incomprehensibl e to me. Some of the clocking schemes in this part are very complicated. I think I need to go back to school and really understand SDC.
Can anyone recommend a good "Theory and Practice" document for SDC timing c onstraints?
Thank you for any advice.
Pete Dudley