Field-Programmable Gate Arrays

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Standards in the real world: UWB

A Comment: http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=YZXW2V41IVXLGQSNDBESKHA?articleID=177100256...
0 comments posted 20yrs
posted by austin
0 comments posted 20yrs posted by austin

Xilinx Virtex-4 RAMB16

Hello group, I have used the new ISE 8.i simulator (nice propeller) to simulate a 9 bit read-only-memory using a BRAM16...
0 comments posted 20yrs
posted by bradsmallridge
0 comments posted 20yrs posted by bradsmallridge

Spartan3 initialization with DSP

Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking to connect the CCLK and DIN pins to the serial...
6 comments posted 20yrs
posted by marco
6 comments posted 20yrs posted by marco

CPLD serial buffer problem

Hi, I interfaced a USB 8 bit data bus with a CPLD. I made a 48 bit buffer ( ser_buff ). I am loading the buffer at each...
0 comments posted 20yrs
posted by conphiloso
0 comments posted 20yrs posted by conphiloso

Unassigned pins

Hello, I have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It is connected to AHC573 latch output...
2 comments posted 20yrs
posted by Jaroslaw.Pawelczyk
2 comments posted 20yrs posted by Jaroslaw.Pawelczyk

Virtex 4 : Configuration-memory readback

Hi, I need to perform configuration-memory readback on an active (not shutdown) virtex 4 device. Does anyone know if on...
0 comments posted 20yrs
posted by bessler
0 comments posted 20yrs posted by bessler

S3e slower than S3

Hi I wonder if anyone (Xilinx?) has actual information on Spartan3e fabric speeds? I have done some actual measurements...
14 comments posted 20yrs
posted by antti
14 comments posted 20yrs posted by antti

FIFO in SDRAM

Hello, We need to implement a FIFO using an SDRAM within a V2PRO. I guess this function already exists, so does someone...
11 comments posted 20yrs
posted by t
11 comments posted 20yrs posted by t

PCI arbiter doubt

Hi , I have got a basic doubt in PCI arbiter regarding the GRANT signal of the PCI arbiter. When exactly should the PCI...
2 comments posted 20yrs
posted by praveen.kantharajapura
2 comments posted 20yrs posted by praveen.kantharajapura

OT: BGA chip test sockets for sale

I have a quantity of various BGA Test sockets, made by Plastronics, Yamaichi and Loranger that are all surplus to requi...
0 comments posted 20yrs
posted by dave
0 comments posted 20yrs posted by dave

Getting Gate Counts from Quartus

Is there any way to get gate counts for a Quartus implemented design? I know Xilinx will give gate counts out of place...
4 comments posted 20yrs
posted by aelbirt
4 comments posted 20yrs posted by aelbirt

Migrating Project from Xilinx ISE 4.1 to 8.1?

Got a project from a consultant using ISE 4.1 but of course the latest download is 8.1. If it matters, target device is...
6 comments posted 20yrs
posted by midicad2001
6 comments posted 20yrs posted by midicad2001