Latest threads in Field-Programmable Gate Arrays

[RANT] Webpack 8.1 editor totally messed up ?

I already saw the message from Antti about '|' char on German keyboard. So I installed WebPack 8.1 with some trepidatio...

11 20yrs

removethis_pasini.a

11 20yrs removethis_pasini.a

Standards in the real world: UWB

A Comment: http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=YZXW2V41IVXLGQSNDBESKHA?articleID=177100256...

0 20yrs

austin

0 20yrs austin

Xilinx Virtex-4 RAMB16

Hello group, I have used the new ISE 8.i simulator (nice propeller) to simulate a 9 bit read-only-memory using a BRAM16...

0 20yrs

bradsmallridge

0 20yrs bradsmallridge

Spartan3 initialization with DSP

Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking to connect the CCLK and DIN pins to the serial...

6 20yrs

marco

6 20yrs marco

How to set Xilinx compiling parameters to get PCI setup time right

Hi, I recently switched from Xilinx 6.3 to Xilinx 7.1.i4. After the first compilation, I was surprised to find that PCI...

3 20yrs

wtxwtx

3 20yrs wtxwtx

CPLD serial buffer problem

Hi, I interfaced a USB 8 bit data bus with a CPLD. I made a 48 bit buffer ( ser_buff ). I am loading the buffer at each...

0 20yrs

conphiloso

0 20yrs conphiloso

xilinx free Sample Pack info now also on Xilinx own webpages

finally the free Sample Pack info is available from Xilinx directly http://www.xilinx.com/products/boards/s3esamplepack...

9 20yrs

antti

9 20yrs antti

Unassigned pins

Hello, I have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It is connected to AHC573 latch output...

2 20yrs

Jaroslaw.Pawelczyk

2 20yrs Jaroslaw.Pawelczyk

Virtex 4 : Configuration-memory readback

Hi, I need to perform configuration-memory readback on an active (not shutdown) virtex 4 device. Does anyone know if on...

0 20yrs

bessler

0 20yrs bessler

S3e slower than S3

Hi I wonder if anyone (Xilinx?) has actual information on Spartan3e fabric speeds? I have done some actual measurements...

14 20yrs

antti

14 20yrs antti

FIFO in SDRAM

Hello, We need to implement a FIFO using an SDRAM within a V2PRO. I guess this function already exists, so does someone...

11 20yrs

t

11 20yrs t

PCI arbiter doubt

Hi , I have got a basic doubt in PCI arbiter regarding the GRANT signal of the PCI arbiter. When exactly should the PCI...

2 20yrs

praveen.kantharajapura

2 20yrs praveen.kantharajapura

OT: BGA chip test sockets for sale

I have a quantity of various BGA Test sockets, made by Plastronics, Yamaichi and Loranger that are all surplus to requi...

0 20yrs

dave

0 20yrs dave

Getting Gate Counts from Quartus

Is there any way to get gate counts for a Quartus implemented design? I know Xilinx will give gate counts out of place...

4 20yrs

aelbirt

4 20yrs aelbirt

Just want to program Xilinx CPLD device from JEDEC file using ISE8.1

As I mentioned in another thread, I received a project from a consultant who supplied the design files, in fact everyth...

15 20yrs

midicad2001

15 20yrs midicad2001

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