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Unassigned pins

Hello,

I have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It is connected to AHC573 latch output pins. In the test phase pins of CPLD are unassigned, and 573 has ca. 0,xxx on the output ( 5 on input), and is getting hot quite fast. First I thought that the chip is broken so I have desoldered it and now with 2nd latch I have the same results. So I thought that it is result of unassigned CPLD pins. Is it true ? (configured as outputs with 0 by default ???)

BTW. I'm using Quartus II 5.1

Reply to
Jaroslaw Pawelczyk
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Hi

Jaroslaw Pawelczyk a =E9crit:

are

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This is a very common problem: by default, QuartusII (and before QII, Max+PlusII) drives unassigned pins to ground. Just uncheck the option and recompile the design. I get stung by this on half my projects and I still don"t understand why Altera keeps this default behavior.

Nicolas

Reply to
Nicolas Matringe

Thank you, I was quite angry when I found out about it. I desoldered 573 once, burned up one of SMD pads for it, got it repaired and lost two days because of it !!! Maybe pulling to ground all unconnected pins reduce noise ?

Jarek

Jaroslaw Pawelczyk a écrit:

This is a very common problem: by default, QuartusII (and before QII, Max+PlusII) drives unassigned pins to ground. Just uncheck the option and recompile the design. I get stung by this on half my projects and I still don"t understand why Altera keeps this default behavior.

Nicolas

Reply to
Jaroslaw Pawelczyk

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