just for fun I wrote down how I see it possible to have different FPGAs to be cut out from single wafer covered with completly repeating pattern
I am not including the text here as I may edit the original even before the post is appearing in the NG
just for fun I wrote down how I see it possible to have different FPGAs to be cut out from single wafer covered with completly repeating pattern
I am not including the text here as I may edit the original even before the post is appearing in the NG
-- Antti Lukats http://www.xilant.com
Antti:
How did you get that site to look like a Wikipedia site? I love it!
-Eli
thats REAL easy, just upload mediawiki files and run admin\install.php :)
if you (or someone else) is looking for web presence provider (web server, database, CVS, etc..) then our server is underloaded and has lots of free space, I am having trouble to fill the 40GB disk space and traffic quato is also not used at all
-- Antti Lukats http://www.xilant.com
guessed correctly. its the only wiki that makes sense. I have tried many different, some other may have some other nice features, but MediaWiki really is the one to use
-- Antti Lukats http://www.xilant.com
Xilinx must be close to this, with their "strip FPGAs" they do now which are BGA only, flip chip.
What about communication between clusters - you don't really want to lock that into PCB routes ? Perhaps a transputer type serial highway, with some redundancy ? Next would be some means of BadCell bypass.
Packages would be a problem - anything over ~20mm/side is prone to cracking : Max die sizes have NOT changed much at all. [Which is also why the rush to 450mm wafers is slower ]
Something with gaps to allow slice, would have less logic inside that Max die area, than a custom die ?
-jg
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