Spartan3 pullups

Hi,

We have several products that use S3's, with a number of fpga pins connected to dipswitches. The dips switch to ground, and we program the fpga's to provide internal resistive pullups.

Some small part of the time, at random, one (typically) pin will fail to pull up, and we have to replace the fpga to fix it.

Anybody else observe this?

John

Reply to
John Larkin
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I don't have the datasheet in front of me, but I believe that Xilinx do not guarantee a minimum pullup current, merely that the pin will be pulled up if it has no external load.

You have an external load.

They used to guarantee a minimum of 25uA (for 3.3 or 5V parts?), but presumably they droppped this specification because of designers forgetting about leakage currents on their boards (or more likely, leakage currents into tri-state outputs on other chips).

In your case, the failure is likely to be because of leakage currents on your board (due to insufficient cleaning) or perhaps capacitvely coupled crosstalk (if the problem is transient in nature).

Moral: read and understand the datasheet, and use pullup resistors where they are needed.

Regards, Allan

Reply to
Allan Herriman

An open dipswitch is a load? Is a pad a load?

If any of these boards leaked even 1 nA, we couldn't sell them. But they don't. And it's not transient.

I used pullup resistors; Xilinx provided them. They're in the databook and the ISE software. If they can't pull up an open circuit, they shouldn't be documented.

John

Reply to
John Larkin

Just out of curiosity, on a failed part, if you add an external pullup resistor, does it start working again? If you look at a failed pin with a scope, what level do you see?

John Providenza

Reply to
johnp

You bet! Almost all the DIP switches I've seen quote an insulation resistance of 100Mohm minimum. 3.3V/100Mohm = 33nA max leakage.

If the pullups are not pulling up, then you must have leakage somewhere pulling them down.

Yes, they're "The optional pull-up and pull-down resistors are intended to establish High and Low levels, respectively, at unused I/Os." ^^^^^^^^^^^^^^ Yours are not unused.

Cheers, James

Reply to
James Kennedy

You could get a uA multi-meter, and check the pins that work, and compare them with the one(s) that don't. Also check the voltages.

That will give you some numbers on the actual effect - It's an analog world - how weak is too weak ?.

You could also create a special test pattern, that does waveform out to the DIP pins, and verify the bonding and IO are intact.

Are these instant failures, or did they work once, and then fail ?

ESD events dump energy into the pins, and I'm not sure if they'd bother to include the pullup fets in the energy radar - these are normally such Hi Z - but they could be a failure point for ESD.

-jg

Reply to
Jim Granville

You should be fine using the internal pullups for DIP switches, as S3 has much lower pullup values than did the older families. Although nominally for S3E, the following document has some additional info on S3 pullup and pulldowns (p60), along with other power and ESD info:

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Things I'd check:

Is there a series resistor or snubber to protect against statically charged fingers pushing the DIP switches?

Is the dead pin completely dead, or does it still work if you drive the input pin high, or configure it as an output with another bitstream?

Have there been any power supply sequencing, phantom power, or configuration issues observed with those boards? ( i.e., could that pin ever have acted as an output or a sneak rail path to a hard ground at some point )

Are any of the dead pins dual-purpose config pins in one of the configuration modes?

Brian

Reply to
Brian Davis

Beginning with the Spartan-3 FPGA family, Xilinx started specifying the pull-up and pull-down currents in the data sheet. For Spartan-3 FPGAs, take a look at Table 6 on PDF page 55 in the Spartan-3 Data Sheet link shown below.

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The pull-up and pull-down resistors in Spartan-3 are quite a bit stronger than in previous families. For 3.3V standards, the pull-up resistor ranges from 1.2K to 4.1K and the pull-down resistor ranges from 1.75K to 9.35K. Spartan-3E toned down the resistance a bit.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Reply to
Steve Knapp (Xilinx Spartan-3 Generation FPGAs)

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