Die Area

I performed a similar search a couple of years ago and came up with little. I believe the FPGA companies don't want people to know exactly how big these dies are in comparison to ASICs.

I was, however, able to get some information from Semiconductor Insights

for use in a paper, provided that I referenced them. They dissect chips and sell reports on them. You can try contacting them, but they will only know the sizes of a few parts that they examined. It should be straightforward, however, to extrapolate to other devices.

They told me that the xc2vp20 was 14.0mm x 11.4mm = 160 mm2 in a 130 nm process.

This compares to a Pentium in the same process with dimensions 12.2 mm x 12.0mm = 146mm2, and a Pentium Prescott, in a 90 nm process, with an area of 10.8mm x 10.3mm = 111 mm2. So you can see why perhaps Xilinx is mum about die sizes. A smaller 2vp part is bigger than a P4 in the same process.

Hope this helps, Stephen

I have made (wild) estimates of die size for all Xilinx products here:

Have fun, Philip

Philip Freidin Fliptronics

Why is there a reluctance to publish accurate die area information?

Some purchas> Hi Guys

1) Nosiness;

2) It tells us how much the die costs you, and whether the chip is likely to get to a reasonable price in the longer term;

3) It's a more useful metric than 'gate count' when comparing to ASICs and other FPGA vendors.

I'd say Curiosity, to sound more positive

As I mentioned, that might not be an accurate measurement. Intel microprocessors are much more expensive per square mm.

I violently disagree! FPGA chip size is inevitably larger than an ASIC of comparable functionality, but the FPGA offers so many advantages that often compensate for its larger size. And FPGAs are made in large volume, and are reconfigurable, ASICs are much smaller volume per design. etc Well-known arguments... Peter Alfke

Steady on!

I'm not complaining about FPGAs; horses for courses. My point is that I know, to a fairly high degree of precision, what I can fit on a square mm of process X. However, I have very little, if any, idea of what I can fit on a square mm of an FPGA. All I have are your marketing gate counts, and I can't turn those into areas anyway. Your gate counts aren't the same as any other vendor's gate counts, and your gate counts will change between devices and generations anyway. The only hard metric is die size. If I know that I can implement something on a 50 mm2 ASIC, but that would take a 250 mm2 FPGA from one vendor, and a 400 mm2 FPGA from another vendor, then that would be interesting, and maybe even useful.

Paul, I hear you, and I have no reason to sound defensive. But your idea just does not work. And will never work. Some areas of an FPGA chip are every bit as efficient as an ASIC, sometimes even more so. Using a better and newer technology (90 nm), certain sections in FPGAs are more compact than ASICs using their 130 or 150 nm technology, because ASICs usually cannot afford state-of-the-art technology. Our BlockRAMs are efficient building blocks, so are the PowerPCs, and the multipliers, and the clock managers, and the input SERDES, and some other dedicated circuits. But then you have the configurtion storage and the generous interconnect structure that ASICs either avoid or can do more frugally.

There is no factor that you can use.There is no 1:1 or even 1:n. And there never will be. Your complaint about gate counts is widely shared, but if you just treat it as number, you can very well compare FPGAs against each other, even between manufacturers. The error will mainly be due to variing percentage usage of the efficient block I mentioned above. You will never be able to say that x square mm of Xilinx, or y square mm of Altera equals z square mm of a certain gate array. So why go to the frustrating exercise? You have to dig far deeper to do an evaluation. And to top it of: the FPGA vs Gate Array choice is mainly not based on area, but rather on total cost. We will never run out of silicon, but the ASIC fan may run out of money... Peter Alfke, from home.

Peter -

One reason to want to know the size is just to be impressed with how much stuff gets fit into such a small piece of silicon. It would be interesting to know from a historic perspective just how things have changed.

How big was a 7400? a 74181? a Z80? a Xilinx 2064 (that was your 1st FPGA?)? a 16L8? etc...

How much more logic is really getting crammed into the silicon today....

The desire to try to find the "actual" number of gates in an FPGA is silly. It will depend on how CLBs are used, if you can fit SRL16's into your design, etc.

I think knowing the actual size is just fun from a gee-whiz perspective.

John Providenza

So, I bet everyone who posts on this board has got a dead or old FPGA lying around somewhere. Although probably fewer than half of us have fuming nitric acid lying around, I also bet we've all got hammers. I'd suggest a ball pein for this particular de-encapsulation job. Is there an EULA for the parts? Cheers, Syms. ;-)

Actually, someone needs to find an old 1702 (??) eprom, one of the original Intel 1 Kbit parts that was UV erasable. How big was the die on that "mega-part"? Which current Xilinx die takes the same area.

One Xilinx BRAM has more capacity than the entire 1702. Of course, I'm comparing ram vs rom here.

As I recall, the programming voltages were amazing. Pull this to 70V, pull that to minus something. Pray that the power transistors on the programmer don't blow out again. Gasp, I'm dating myself!

John Providenza

Yes, and the first computers used two triode vaccuum tubes to store a bit, with a supply voltage around 150 V.

60 years of Progress ! Peter Alfke

I was just admiring the pretty white and gold package on a 1702A I came across in one of my old project junk boxes last week. Those were pretty parts. I don't miss the programming though. I don't recall 70v, I think it was more like -48v and that needed to switch from 0 to -48 for the programming pulse, and there was also a substrate voltage of something like -40v, that also had to be pulsed. The data and address also had big voltages on them, I don't recall if they were -40 or -48v. Even reading this was a bit of a pain because it needed a bias voltage of --9v. Still, they were very pretty chips to look at.

BTW, the die looks to be about 3/8" square.

Gasp, I'm dating myself!

So, is that 1702 the part number, or the date code ? ;)

-jg

Jim,

1702 is a part number, but I would think you know that? or are you really younger than I ?

Antti

here's a few:

-- Mike Treseler

Actually, the 1702A was a 2K bit part, organized as a 256x8. Here's a data sheet

Mike, the ones in your pictures sure aren't as pretty as the one I was looking at the other day. Mine is in the white cermic package with the gold pins and gold around the window. There is one like it on the board in your first picture in the middle of the 3 PROMs there.

That shows RAMs and ROMs, but I didn't see any shots of EPROMs, at least with the window uncovered to allow us to dimension the die.

There are a few shots of some 1702s here though:

Using the 100 mill pin pitch for scaling, I'm getting a die size of about .14 x .11 inches, which gives an area just under 10 square millimeters.

--
    Later,
    Jerry.

Colossus used (afair) 4 pentodes: 2 for the flipflop, and 2 more to switch it, essentially wire-ANDed to each of the F/F tube anodes. They made each of the switch tubes act as a 2-input AND gate, using the control & screen grids independently (& at different voltage levels). Why pentodes? They were already being produced in vast numbers, for radio & radar. Triodes had much less use in that sector.

An anecdote has it that when the truck driver went to requisition yet another truckload of EF36 tubes (but didn't know what they were for), the storeman asked him "what are you doing with those things? Shooting them at the Jerries?" :-)

Quick answer: find a friendly dentist, & have him X-ray the package in question. That's what we did at work many years ago (I no longer work at that company), when we wanted to examine (non-destructively) a competitor's product.