Field-Programmable Gate Arrays

Simulation of MicroBlaze embedded system

Is there a guide to behaviorally simulating a MB embedded system? I have gotten as far as compiling the libraries, runn...

5 comments posted 20yrs

posted by mottoblatto

5 comments posted 20yrs posted by mottoblatto

ModelSim # Error loading design

I just downloaded Xilinx ISE 8.1 and ModelSim XE III/Starter 6.0d I make a simple project, using schematic (one and gat...

6 comments posted 20yrs

posted by no

6 comments posted 20yrs posted by no

Xilinx ISERDES Q1 issues

I am getting strange results in the Xilinx ISERDES Q1 output. Specifically it will sometimes be almost random values. A...

2 comments posted 20yrs

posted by bradsmallridge

2 comments posted 20yrs posted by bradsmallridge

Lattice new ECP2 parts

Seems these are too new to even be in production, but they are very interesting. Anyone have any pricing on them yet? I...

0 comments posted 20yrs

posted by spamgoeshere4

0 comments posted 20yrs posted by spamgoeshere4

Need help with generating video patterns using VHDL

Hi, I am currently working on generating digital video using an FPGA. I am using VHDL to generate color bars and other...

4 comments posted 20yrs

posted by gmethi

4 comments posted 20yrs posted by gmethi

Lattice high-end devices announced after years of rumours...

We've been waiting for these for a while now, but looks like it may be worth the wait... http://www.latticesemi.com/prod...

0 comments posted 20yrs

posted by gabor

0 comments posted 20yrs posted by gabor

OPB busmaster device

Hi I just created a design with a µBlaze and some LEDs for testing and a OPB Busmaster device created with the xps help...

0 comments posted 20yrs

posted by st

0 comments posted 20yrs posted by st

EDK - PLB/OPB Bus questions.

Hi all, I have some questions regarding the PLB and OPB busses used in EDK. 1) Is it true that a bus arbiter is needed...

8 comments posted 20yrs

posted by me_2003

8 comments posted 20yrs posted by me_2003

vhdl to edif

Hi, may I know whether there is any free program that is able to convert a vhdl file to a .edf file? I am unable to fin...

9 comments posted 20yrs

posted by nordicelf

9 comments posted 20yrs posted by nordicelf

Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?

Gurus, I have built and tested a numerically-controlled oscillator (clock generator) using a simple phase accumulator (...

17 comments posted 20yrs

posted by peter

17 comments posted 20yrs posted by peter

Which workstation or server should I take to build a state-of-the-art FPGA CAE tool workstation?

I was wondering which PC configuration is the best for: Running ISE Running Modelsim Running Synplify Premier Just to s...

1 comments posted 20yrs

posted by electronics_designer

1 comments posted 20yrs posted by electronics_designer

Async Processors

Further to an earlier thread on ASYNC design, and cores, this in the news : http://www.eet.com/news/design/showArticle....

47 comments posted 20yrs

posted by no.spam

47 comments posted 20yrs posted by no.spam

Virtex4 Powerdown, Vcco questions

Hi *, I'm planning a device with a backup battery. In case of power failure, the FPGA (a Virtex4 in this case) should b...

2 comments posted 20yrs

posted by smd

2 comments posted 20yrs posted by smd

MicroBlaze in Spartan 3 playing tuxchess :)

Hi having MicroBlaze to boot uClinux to command prompt sure is nice also but seeing it running graphical tuxchess is ev...

5 comments posted 20yrs

posted by Antti.Lukats

5 comments posted 20yrs posted by Antti.Lukats

Open Verification Libiary Free Download

Hi all, I am a Verilog user and I want to find some tools do assertion(like C's assert()). I found Open Verification Li...

3 comments posted 20yrs

posted by zhushenli

3 comments posted 20yrs posted by zhushenli