Gurus,
I have built and tested a numerically-controlled oscillator (clock generator) using a simple phase accumulator (adder) and two registers. One register contains the tuning word (N), and the other is used in the feedback loop into the second input of the adder.
I take the MSB of the feedback register as my synthesised clock. I am generating sub 50kHz clock frequencies, by clocking the feedback register at 100 MHz. The accumulator is a 32 bit adder as is the feedback register (of course). Works nicely on a board (my tuning word comes from a processor chip, and my spectrum analyzer tells the truth when I look at my MSB generated clock).
To reduce the jitter I would like to run two or more phase accumulators in parallel which are clock-enabled on every-other clock cycle (as per Ray Andraka's suggestion from the "how to speed up my accumulator" post by Moti in Dec 2004) and then switch between the MSBs of each accumulator using a MUX on the MSBs.
The problem then comes down to how fast I can switch the MUX - the faster the better.
- Is the Xilinx CoreGen 1-bit MUX a good option?
- For a 4-input 1-output MUX I would need a 2 bit counter counting the select word in sequence 00, 01, 10, 11, 00 .... - how fast could this be done?
- What about using a fast parallel-to-serial converter approach ? (feeding the outputs of each NCO into a shift register and then blasting out the bits really fast to a pin - effectively doing a round-robin type switching between the MSB of each NCo).
I have designed (but not yet implemented) this scheme, and I would like some advice relating on how best to best do this.
I look forward to everyone's replies!
Cheers, PeterC.