Field-Programmable Gate Arrays

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How to gnerate VCD file with hex outputs.

Hi all, I am trying to generate a vcd file from the model sim V6.0a. tried the following command vcd file test1.vcd vcd...
2 comments posted 20yrs
posted by vssumesh_asic
2 comments posted 20yrs posted by vssumesh_asic

DK: Interfacing Handel C and VHDL

Hi, I have been trying to make an example work in the DK Design Suite but to no avail. Can anyone who has experience in...
0 comments posted 20yrs
posted by nordicelf
0 comments posted 20yrs posted by nordicelf

I2C timing problem

hi! i am developing i2c master in FPGA. suppose ia m transmitting 1. i have doubt whether data transition should be at...
1 comments posted 20yrs
posted by hyankijitu
1 comments posted 20yrs posted by hyankijitu

ISE Simulator

How do you add signals within your VHDL architechture using Xilinx 7.1 ISE Simulator? Brad Smallridge aivision dot com
3 comments posted 20yrs
posted by bradsmallridge
3 comments posted 20yrs posted by bradsmallridge

Spartan3 Live Insertion with XC9572XL chip

Hi everyone, Ive got some questions about live insertion of S3 chips. I am designing an fpga module as well as a daught...
0 comments posted 20yrs
posted by jaxato
0 comments posted 20yrs posted by jaxato

latest XILINX WebPack is totally broken

I recently "upgraded" three of the systems here to use v8.1 of the XILINX ISE WebPack software, and its companion MXE s...
10 comments posted 20yrs
posted by richard
10 comments posted 20yrs posted by richard

Re: Verilog 2's Complement Shifter

WHY do Verilog users post in this newsgroup ? Rgds Andrés Why do responders keep the full cross-post list? - John_H
0 comments posted 20yrs
posted by johnhandwork
0 comments posted 20yrs posted by johnhandwork

Microblaze Virtual platform problem

Hi, I'm trying to simulate my microblaze sw/hw using the virtual platfrom feature. The problem is that when i try to ge...
1 comments posted 20yrs
posted by me_2003
1 comments posted 20yrs posted by me_2003

why does speed grade effect VHDL program??

Hello I recently designed a basic serial in parallel out IO board that used an Altera MAX 7128slc84-10 chip. I was able...
23 comments posted 20yrs
posted by clement
23 comments posted 20yrs posted by clement

input signals in ISE simulator

Hi, why in ISE simulator (version 7.1 sp4) I'm only able to change input signal value on falling edges of the clock (bo...
1 comments posted 20yrs
posted by marco
1 comments posted 20yrs posted by marco

Software reset for the MicroBlaze

Hey all, I was wondering how to write a software reset in C-code for the Xilinx Microblaze. Regards Karel
6 comments posted 20yrs
posted by karel
6 comments posted 20yrs posted by karel

Microblaze using SPI flash as instruction memory

Hello, I have the following system: - A Spartan 3E 500 FPGA - Some internal BRAM memory - An external SPI flash The ext...
6 comments posted 20yrs
posted by Karel.Deprez
6 comments posted 20yrs posted by Karel.Deprez

Xilinx Spartan 3 LVDS Misbehaving

Greetings FPGA Group, I'm attempting to input an LVDS clock signal into a SoC design. This development is based on a Nu...
1 comments posted 20yrs
posted by aroldao
1 comments posted 20yrs posted by aroldao

doubt

Hi How to map a desgin on to FPGA by using qautus tool.i am knew to this one .to map a desgin in to FPGA .what are the...
1 comments posted 20yrs
posted by kvs_456skec
1 comments posted 20yrs posted by kvs_456skec