Spartan3 embedded synchronous multipliers

Yes,

Aust> Hi guys, I've been reading through the Spartan3 architecture embedded

No asumption is safe, IHMO, run a simple simulation to verify it, sometimes that's quicker than digging in the docs jungle.

I'm assuming that you're reading XAPP467. Is this correct?

In Spartan-3, there is a single pipeline stage option between the multiplier inputs and outputs. Essentially, the stage is after calculating the partial sums and before presenting the product output.

In Spartan-3E, you have the additional option for a single- or double-stage pipeline. In Spartan-3E, the pipeline state is either at the inputs or at the product outputs, or both.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Yes,

That is the app note I have read. So the unit is pipelined. Alright, so I should account with it by allowing 2 cycles? (1 for the data to propogate through partial sums muxes and another for the adders to obtain the product and to present the output?)

Note the word "option". You can run pipelined or not pipelined. Obviously the clock rate must be lower in the non-pipelined mode. But there you get the result out with just a combinatorial delay. Peter Alfke