Field-Programmable Gate Arrays

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spartan3 starter kit.

a really stupid question.... so general purpose ports/pins. where are they on the spartan 3 starter kit? so i read that...
9 comments posted 20yrs
posted by zhangweidai
9 comments posted 20yrs posted by zhangweidai

Spartan3 configuration

Hello, I would like to configure a Spartan 3 device (3S200) using its parallel slave interface mode. Unfortunately, I c...
0 comments posted 20yrs
posted by wyderski
0 comments posted 20yrs posted by wyderski

schematic capture

what is a good schematic capture program that is compatible with Xilinx ISE? Does OSR exist? optical schematic recogniti...
0 comments posted 20yrs
posted by aiiadict
0 comments posted 20yrs posted by aiiadict

Simulation problem using CONV_INTEGER

I have the following code: signal busy_condition : std_logic; signal high_registered : std_logic_vector(1 downto 0); si...
2 comments posted 20yrs
posted by giovanniparodi79
2 comments posted 20yrs posted by giovanniparodi79

using FPGA in control field

Hi all, I want to use FPGA in control field. I know that uC or DSP processor is a preferable choice to control engineer...
9 comments posted 20yrs
posted by wicky.zhang
9 comments posted 20yrs posted by wicky.zhang

LVDS

I am routing a pcb with a fpga and adc which has LVDS outputs. I am tryin to match the length of the signals. Will I be...
3 comments posted 20yrs
posted by maxascent
3 comments posted 20yrs posted by maxascent

Creating low freq. clock on Altera FPGA

Hello all, I have to create a low speed clock (8KHz) out of a high speed one (50MHz) on an Altera FPGA (Cyclone II). It...
2 comments posted 20yrs
posted by avishorp
2 comments posted 20yrs posted by avishorp

Using Ethernet to control/initialize FPGA

Add an Ethernet MAC to your FPGA to enable control from a PC. Simple & easy. No driver programming. Direct control of F...
0 comments posted 20yrs
posted by james.ma
0 comments posted 20yrs posted by james.ma

SMP on virtex-ii pro

Hi, I'm trying to enable SMP for a virtex-ii pro board. PPC doesn't support cache coherency, but that won't be an issue...
1 comments posted 20yrs
posted by dasani8888
1 comments posted 20yrs posted by dasani8888

SHARCS 2006

We apologize for multiple mailings. ====================================================================== SHARCS -- Sp...
0 comments posted 20yrs
posted by tanja.lange
0 comments posted 20yrs posted by tanja.lange

Spartan-3 Serial LVDS max speed?

The Xilinx App Note, xapp224, suggests that it's possible to do non-source-synchronous data recovery in a spartan-3 at...
0 comments posted 20yrs
posted by jonas
0 comments posted 20yrs posted by jonas

Altera EPLD

In a project I use the Altera EPM3256ATC144-10. Now I have the necessity to make some changes to the project, but I don...
10 comments posted 20yrs
posted by dev2-renato_noSpam
10 comments posted 20yrs posted by dev2-renato_noSpam