Creating low freq. clock on Altera FPGA

Hello all, I have to create a low speed clock (8KHz) out of a high speed one (50MHz) on an Altera FPGA (Cyclone II). It has to be a real clock, not a clock enable. PLL is of course out of question because this frequency is out of its range. Trying to generate it with a simple couter generates many warning, and in some cases Quartus reports that the design does not meet time constraints. I tried to designate the generated signal as a clock, but it doesn't improve the situation. Is there another, "correct" way for doing this? Maybe I should insert some kind of buffer after the counter? I would appreciate your advice.

Thanks, Avishay Orpaz