Field-Programmable Gate Arrays

VHDL to create LUT based delay

I'm looking to create a LUT based delay line for use in aligning DDR strobes. The target device is a V2P, I have read t...

6 comments posted 20yrs

posted by billingworth

6 comments posted 20yrs posted by billingworth

Loop Optimization

Hi all! I' using Handel-C to target hardware (a board with spartan IIE) and i'd like to optimize this following macro (...

0 comments posted 20yrs

posted by gioeroby

0 comments posted 20yrs posted by gioeroby

A dev board supporting partial/dynamic reconf.

Hello, Could U please suggest me a development board which really supports partial/dynamic reconfiguration, satisfying...

6 comments posted 20yrs

posted by sec_lab

6 comments posted 20yrs posted by sec_lab

V4 FIFO16 and SRAM

Hello Group, I could use some advice on hooking up asynchonous FIFO16s to an SRAM interface. Specifically I have two FI...

17 comments posted 20yrs

posted by bradsmallridge

17 comments posted 20yrs posted by bradsmallridge

How about a "File Exchange" for System Generator designs?

Just a thought. I think it would be very useful if there was a section of the Xilinx website for exchanging reference d...

0 comments posted 20yrs

posted by bgaughan

0 comments posted 20yrs posted by bgaughan

Module-based partial reconfiguration in ISE Webpack

Hello, I'm a newbie in partial reconfiguration and I'm using the tutorial by Gregory Mermoud "A Module-Based Dynamic Pa...

2 comments posted 20yrs

posted by frr

2 comments posted 20yrs posted by frr

FPGA Selection Question

Hi I am using a 8-bit ADC with parallel LVDS outputs clocked at 250MHz. want to interface this to a FPGA, then place th...

6 comments posted 20yrs

posted by maxascent

6 comments posted 20yrs posted by maxascent

Problem after P&R using Xilinx Viterbi Decoder IP

Hello all, I'm using the Xilinx Viterbi decoder IP (V5) in serial mode with standard parameters (conv 7 1/2 with codes...

0 comments posted 20yrs

posted by arivaton

0 comments posted 20yrs posted by arivaton

[EDK] XilNet throughput

Hello all, I'm using the XilNet library on a Virtex-II Pro (PPC), and my objective is to send quite large amounts of da...

2 comments posted 20yrs

posted by xjohbex

2 comments posted 20yrs posted by xjohbex

System Packet Interface?

Hi, I am doing a project on a 10GB Ethernet. I am going to use a FPGA with a 10Gb Ethernet Mac Core. If I use a NIOS II...

1 comments posted 20yrs

posted by freechip

1 comments posted 20yrs posted by freechip

implement IP TCP Layer in FPGA

Hi, I want to implement IP and TCP Layer in FPGA. I don't know if some of you have done something about this implentati...

2 comments posted 20yrs

posted by freechip

2 comments posted 20yrs posted by freechip

a master-IPIF problem on the PLB bus

Hi, group I generated a IPIC interface with the "Create and Import Peripheral Wizard" in EDK's XPS to acces BRAM on the...

0 comments posted 20yrs

posted by michiel.vanderlinden

0 comments posted 20yrs posted by michiel.vanderlinden

The 95108 cpld is getting heated when connected by CRO

I have xilinx 95108 I am clocking by 555 timer and testing for some small project. the 95108 is getting heated up when...

8 comments posted 20yrs

posted by devendra.bhale

8 comments posted 20yrs posted by devendra.bhale

PPC405 - FPGA interface design

Hi I am trying to design a PHY-MAC interface on a Virtex-2 Pro FPGA. The MAC will be running on PPC 405, and the the PH...

1 comments posted 20yrs

posted by amitshukla1979

1 comments posted 20yrs posted by amitshukla1979

Need a SPI 4?

Hi I am working on 10 Gb Ethernet project. I am going to use a NIOS II in a Stratix II or a Stratix GX. I don't kno yet...

1 comments posted 20yrs

posted by freechip

1 comments posted 20yrs posted by freechip