Field-Programmable Gate Arrays

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Broaddown4 - Ultimate Virtex-4 Development Board

We have been talking about Broaddown4 for a long time and finally you can get the first viewing here http://www.enterpo...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

ISE WebPack and Bitstream encryption

Does anybody know if the ISE WebPack environment support the Bitstream encryption in the Vertex II devices? Thanks ahead...
0 comments posted 20yrs
posted by scot.willis
0 comments posted 20yrs posted by scot.willis

Spartan 3 Expansion Board

I have a Spartan 3 starter kit. Im going to build an expansion board that will have some more components on it. does an...
5 comments posted 20yrs
posted by zhangweidai
5 comments posted 20yrs posted by zhangweidai

Assign FPGA pins to submodule

I'm currently working with ISE 7.1 I'd like to be able to assign FPGA pins to a submodule either via a ucf file, or (pr...
2 comments posted 20yrs
posted by mfornero
2 comments posted 20yrs posted by mfornero

DMA and PCI in SoPC Builder

Hi All, I have some problems using SoPC builder (5.1) with DMA and PCI (Altera PCI compiler 4.1.0). I have system with...
7 comments posted 20yrs
posted by zizka
7 comments posted 20yrs posted by zizka

PPC LUTS registers

Hi i was wondering which would be the best way to get the PPC on a virtex II pro to control the 4 inputs on a LUT, so f...
1 comments posted 20yrs
posted by godzillalad
1 comments posted 20yrs posted by godzillalad

Help wanted

Hi to all Newsgroup, I need of your little help. With an 8 bit microcontroller I must to calculate the AD9558 DDS input...
16 comments posted 20yrs
posted by iz5fcy_NOSPAMPLEASE_
16 comments posted 20yrs posted by iz5fcy_NOSPAMPLEASE_

coregen on webpack 8.1

I have generated a DP ram core in webpack 8.1, and it creates the VHD files and templates. When I synthesize a file tha...
2 comments posted 20yrs
posted by scott.caples
2 comments posted 20yrs posted by scott.caples

rocketio in serdes mode

Hi, Actually i am using rocketio wizard 7.1.I want to do conversion of 8 bi parallel data into serial stream using rock...
0 comments posted 20yrs
posted by mohmedhanif.kagdi
0 comments posted 20yrs posted by mohmedhanif.kagdi

Virtex4 MGTs using Aurora Core

Hi, I am having problems trying to get an Aurora core working in Virtex 4 parts. Has anyone managed to get an MGT worki...
0 comments posted 20yrs
posted by david_easton
0 comments posted 20yrs posted by david_easton

i2c addressing

hi! i want to know that i2c addressing scheme for page write fashion how will it be. i mean what will be address scheme.
1 comments posted 20yrs
posted by hyankijitu
1 comments posted 20yrs posted by hyankijitu

Pulse Shape in a functional simulation

Hello, I have this question and I have no idea if this is a simulator quirck or bad design. I am designing a pulse reco...
12 comments posted 20yrs
posted by saurster
12 comments posted 20yrs posted by saurster

problem with ISE versions

Hi all, I want to use a small cricuit (written in verilog and was designed using ISE 3) in an other project using ISE 8...
5 comments posted 20yrs
posted by mazouz.nezhate
5 comments posted 20yrs posted by mazouz.nezhate

Virtex-4FX Mini Module TEMAC examples

Hallo, has someone found some example about hard temac and how to connect it to plb bus and broadom phy layer of the mod...
8 comments posted 20yrs
posted by marc
8 comments posted 20yrs posted by marc