Pulse Shape in a functional simulation

How do you delay the pulse stream?

Rgds Andr=E9

I pass the input pulses through a shift register. For example, the verilog equivalent is as follows always @(posedge clk3 or negedge reset_n) begin if(~reset_n) begin delay_reg[0:29]

Thanks John, you were right, in my stimulus, the video_in pulses (that is an input) were too close to the clk3 clock edge, however I have another question about this, in my design since i am using clk3 to clock video_in(asynchronous signal) into a shift reg, is a 2-stage synchronizer enough to reduce the effect of metastability on this signal?

If your shift register is implemented as registers instead of SRLs, metastability is taken care of for you. If you are using SRLs, the only caveat is that an intermediate level may be preserved as "uncertain" as it propagates through the SRL; the metastability just moves to the output side of the SRL. So... 2 registers is safest on the input but you could just as easily have those two on the output side of the SRL. Routing distances between 2 synchronizing registers should be given ~2ns slack to provide "exceptional" immunity rather than just "excellent." Things are so much cleaner these days!

Even an SRL does not propagate metastable levels. There is enough gain in each latch to eliminate metastable level in the second latch. The difference between SRLs and "normal" shift registers is that the SRLs use short-time capacitive storage between adjacent latches, while conventional shift registers use a master latch followed by a slave latch. There is a difference between logic uncertainty caused by metastability (which will propagate through any shift register or other sequential logic) and the physically "half-way" level, which does not survive more than one stage. Simulators propgate the X, but that is symbolic. Real flip-flops stay metastable only for up to a few nanoseconds. (Theoretically there is no upper limit, but in our limited lifetime any delay more than a few ns is so improbable that it is statistically insignificant). If you want to play it real safe, make that 10 ns. Peter Alfke, Xilinx Applications.

Doesn't this impose a maximum time for the clock to be in one state, as compared to a fully static approach?

Thanks for the clarification, Peter. Austin lead some of us here (me at least) to believe that the SRL might effectively preserve the intermediate level within the shift operation, pushing the metastability issue to the other side of the SRL.

It's good to know they can eliminate sampling uncertainty in a simple, unconstrained SRL delay chain.

Not externally, but inside the SRL there is (I think) a clock differentiator. The idea is to put a low-pass filter between adjacent latches, and make the transfer pulse so short, that the transfer is only of the old, stable dta, not of the just arriving data. That avoids any race condition. The conventional master-slave flip-flop uses a more brute-force approach that requires two latches. The "low-pass filter, clock differentator" approach was popular 50 years ago, when discrete transistors were expensive, and resistors and capacitors were cheap.

Peter Alfke, Xilinx Applications

Well, there is always the inherent sampling time uncertainty of one period of the asynchronous clock. I would reduce that by using a really fast clock, like 200 MHz+. Peter Alfke

I thought most modern LOGIC devices FlipFlips, were built using transmission gates - which I think is what you are talking about with the SRL's ? eg my classic 74LVC74 data, shows 4 OR gates, and 4 transmission gates.

-jg