Field-Programmable Gate Arrays

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Par error in Spartan-3

I met problem while doing place for Spartan-3 in ISE 7.1 .They said. Number of BUFGMUXs 2 out of 8 25% Number of Extern...
6 comments posted 20yrs
posted by kent.mou
6 comments posted 20yrs posted by kent.mou

Which CPU and Screen Rez for ISE 6.3i ?

I own a notebook 700 MHz PIII / 256 MB / 10.4" / 1024*768. I am thinking of upgrading because ISE 6.3i runs very sloooo...
7 comments posted 20yrs
posted by u1000393
7 comments posted 20yrs posted by u1000393

Question for the EDK ppc users ...

Hi all, my question is as follows, I am now going through a ppc design that I would like to run as follows : I need to...
4 comments posted 20yrs
posted by me_2003
4 comments posted 20yrs posted by me_2003

FpgaC Beta-2 release on sourceforge.net today

http://sourceforge.net/projects/fpgac svn co https://svn.sourceforge.net/svnroot/fpgac/tags/fpgac.1.0.beta-2 fpgac.1.0....
0 comments posted 20yrs
posted by fpga_toys
0 comments posted 20yrs posted by fpga_toys

Hollybush1 - PC104+ Board

Now on our website is our new PC104Plus board Hollybush1. Base board is Spartan-3 based but Virtex support is coming so...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

The IDE interface

I want to know the default pio mode when device reset and powup,and if the udma mode is surported when device reset and...
8 comments posted 20yrs
posted by bjzhangwn
8 comments posted 20yrs posted by bjzhangwn

can I port ppclinux to virtex4-fx?

I have bought ML403 borad with MontaVista linux, but I prefer to ppclinux rather. from my point, it is possible because...
5 comments posted 20yrs
posted by wicky.zhang
5 comments posted 20yrs posted by wicky.zhang

EDK: choices for simple internal control

Dear EDK experts, I have a top-level ISE project with an EDK subsystem. In that top-level design I have a state machine...
11 comments posted 20yrs
posted by mbmsv
11 comments posted 20yrs posted by mbmsv

why use an FPGA when a CPLD will do ??

Hey guys/gals What are the advantages and disadvantages of using a CPLD instead of using an FPGA for a design? Thanks
16 comments posted 20yrs
posted by clement
16 comments posted 20yrs posted by clement

Xilinx Coregen

I am using ISE 8.1.02i webedition and have just installed the MIG 1. coregen. When I try to use it nothing is generated...
2 comments posted 20yrs
posted by maxascent
2 comments posted 20yrs posted by maxascent

bscan_virtex4 device

I am trying to use the jtag interface as a general purpose communication port. I looked at the GNAT module (http://www....
4 comments posted 20yrs
posted by someone
4 comments posted 20yrs posted by someone

Virtex-4FX MiniModule Atmel Flash

Hallo, the Atmel flash memory present on the MiniModule can be used to store software application code? Many Thanks Marc...
7 comments posted 20yrs
posted by marc
7 comments posted 20yrs posted by marc

Simple ADS5273 -> Xilinx Interconnect Model

> > One thing that jumped out at me from the ADS5273 datasheet >was the output slew rate and impedance specs: > > LVDS...
10 comments posted 20yrs
posted by brimdavis
10 comments posted 20yrs posted by brimdavis

Device ID of GPIO

Hi, there I want to use GPIO to control the LED. Before that, I need to use XStatus XGpio_Initialize(XGpio *InstancePtr...
3 comments posted 20yrs
posted by agou.win
3 comments posted 20yrs posted by agou.win

Using time.h in EDK

Hi, I'm trying to measure program execution time in Platform Studio. I use two clock() functions from time.h before and...
1 comments posted 20yrs
posted by dasani8888
1 comments posted 20yrs posted by dasani8888