Which CPU and Screen Rez for ISE 6.3i ?

I own a notebook 700 MHz PIII / 256 MB / 10.4" / 1024*768. I am thinking of upgrading because ISE 6.3i runs very slooooowwwww with this notebook. Not to mention that at 1024*768, nothing much that I can see on the screen. I need higher resolution and faster CPU.

  1. What screen resolution is the ideal one for ISE?
  2. Which screen resolution that you usually use at work?
  3. What is the ideal CPU speed and RAM if I limited my self to an FPGA less than 1.5 M gates with little constraint in the design. Hendra
Reply to
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It really depends on just what you want to do with your gates.

I use a P4 2.6G and am very happy with it. Screen is 1280x1024. I wouldn't consider less these days. There has been talk of Dual processors being the best bet but their best feature is the ability to do something else while the FPGA tools are busy.

If you really want to do FPGA's then first ditch the laptop. You will need RAM and horses. 512M RAM minimum 1G better


Reply to
Simon Peacock

Howdy Simon,

I'm not sure if you are talking about laptops in general, or just his laptop. His laptop is obviously too slow for medium to large designs, but more modern ones, with Pentium M processors, are faster than many P4's, including the 2.6 GHz unit in your machine. And that is despite the Pentium M being based on the Pentium III design!

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Basicly, the MHz race is dieing:

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Both vendors are transitioning to meaningless numbers and letters (Intel's Pentium D "900", AMD's FX series) and to multiple cores. I don't think the race is dieing in just processors, either.

ObFPGA: Anyone notice how only the embedded stuff (DSP block and 405) in lowest speed grade of the V4 got noticeably faster over V2Pro?

Have fun,


Reply to
Marc Randolph
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Anymore, just about any CPU is fast enough to be reasonable. RAM and (particularly) hard drives make a much bigger difference. Even the "desktop replacement" notebooks rarely have anywhere close to the RAM capacity of a decent desktop.

As far as hard drives go, see:

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for one example of a direct comparison of notebook drives to desktop drives. In this comparison, the notebook drives lose by a fairly wide margin -- and these aren't even particularly high-performance desktop drives.

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Reply to
Jerry Coffin

I have 2 machines:

  1. IBM Thinkpad T23, P3M 1.13Ghz, 512MB RAM, 16MB VC (running at
1024x768x32-bit since that is max resolution of my LCD panel). WinXP SP2.

  1. AthlonXP 2500+ @ 2.2Ghz, 768MB DDR, 9600XT 128MB at same resolution, Win2K SP4.

Both machines do well. I use my AthlonXP for Xilinx ISE and my P3 does simulations in ModelSim. My P3 performs very well with simulations, not far off from my AthlonXP machine. Might be that your chip is the older P3. I have the Tualtin core which has 512KB of L2, it still IMHO is a decent performer.

Reply to
Isaac Bosompem

How long is a piece of string? It's more a matter of what you're going to use ISE for, rather than any innate requirements imposed by ISE. You could just as well ask which CPU and screen resolution you need for C++ or Java development; there's no meaningful one-size-fits-all answer.

They don't make one with high enough resolution. Get the best you can afford.

1600x1200 (Samsung Syncmaster 213T 21" LCD). I'm thinking about adding a second of the same, since two of those together only costs about half the price of a 1920x1200.

As fast as you can afford. I'm making do with an Athlon XP 3500+, with

1G of RAM. Usually that's OK, but one of my designs takes six hours to build if I crank up the timing-directed-map effort and P&R effort levels to reach my timing constraints. (I haven't yet tried PlanAhead.) Most of the time I can debug my design without doing that, though, since I can run the prototype hardware at a lower clock rate than the target.
Reply to
Eric Smith

Wow, how big are your designs?!

I guess I havent needed that much power cause I am using an XC3S200 FPGA. I am guessing you are using at least an XC3S500 or larger, depending on your design?

Reply to
Isaac Bosompem

Yes, I'm using an XC3S500. That particular design currently uses about half of the resources of the part. Normally a design that small doesn't take that long to compile, but this particular one has some very large combinatorial functions (the PLA I brought up in another thread).

Reply to
Eric Smith

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