slice macro replace the bus macro in the virtex-4 how to do that?????

hm, at DATE yesterday a university guy who is doing partial reconfig with v2pro claimed that xilinx will come out with v4 partial reconfig solution in one week time, dont know more, but maybe xilinx is really having some new things for v4 reconfig

that is not news to do partial reconfig with v2pro in the module-based , but just you said xilinx is really having some new things for v4 PR but whats the new? and someone in the xilinx said v4 have a new bus macro "slice macro" to replace TBUF macro like " bus macro" but what is hell it?

well all I know is that a person who is doing some university research on xilinx partial reconfig, says that he can not do V4 as of today, but will be able todo withing a week time because xilinx is about to release something withing one week, that what I was told, what it is going to be released (if at all) I dont know.

Hi xun,

you can use a slice-based bus macro, but at this moment, you need to develop it. Of course, as Virtex-4 device has not TBUF the slice-based approach will be used by Xilinx too (I think). I was working with Spartan-3 (it has not TBUFs) and this approach is useful.

About the use of partial reconfiguration in Virtex-4, there are some errors using the ISE tools. As the Xilinx people said in previous messages, they are working on it.

Regards,

Ivan

snipped-for-privacy@gmail.com wrote:

Hello Ivan,

I would like to do a slice-based bus macro.

But i don't know how to do. Could you help me or show me the direction?

Jean-Baptiste

Hi Jean-Baptiste,

you can download a presentation about my work in:

I think it will be useful to understand how to develop slice-based bus macros :)

Regards

Ivan

jean-baptiste wrote:

Hi Ivan,

could you please comment, on your slide 63, how you compute the values for the options PartialMask0,1,2 ?

Thanks

Hello Ivan. For the assured correct coupling what bus macro is it better to use? Probably Hard Macro? I will be very thankful if you were able to lay out separately something like a *.nmc or *.xdl file.

Beforehand thankful.

Hi,

good question!!. I had to read the datasheet information about the frame configuration in Spartan-3...

Regards,

Ivan

Stephane wrote:

Actually, the explanation of these bitgen options in ISE is that it takes in consideration only the major addresses of block type 0,1,2 in hex value... but block types is not described here, and the hex chain generation is not obvious... I think you are refering to the XAPP452 ?

By the way, Jean-Baptiste, you'll find dozens of resources on the web on how to create your macros. The latest one is here:

You create those you want with fpga_editor: add 2 slices, route them automatically, and inside slices, route with the buffers and put wires inside the LUTs, and you're done!

Hi,

Yes. I did not remember that it was an application note ;)

Regards,

Ivan

I want to create macro bus. How I understood, it is necessary in FPGA Editor to add 2 SLICE ("EDIT->ADD"). Then to put together them between itself through node. But not clearly what outputs SLICE_1 is it necessary to conduct node from and on what entrances SLICE_2 ?