Field-Programmable Gate Arrays

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Creating macros

Hi guys, have a question can any1 help me with building a macro????? i have a VHDL design and i have mapped, placed and...
0 comments posted 20yrs
posted by harissh77
0 comments posted 20yrs posted by harissh77

www.buswares.com

register and download ------a professional computer and communication bus forum
2 comments posted 20yrs
posted by water9580
2 comments posted 20yrs posted by water9580

decoding

Dear all Can any one help me to understand LDPC code 1) If LDPC code decode using viterbi algorithm and sum product alg...
0 comments posted 20yrs
posted by shereen.ahmed
0 comments posted 20yrs posted by shereen.ahmed

asynchronous FIFO design

As I have a problem in asynchronous FIFO design. My case is described as below, I want to design a FIFO as write in clo...
3 comments posted 20yrs
posted by kelvins.huang
3 comments posted 20yrs posted by kelvins.huang

C-Compiler for free VHDL controller core ?

Hi ! I would like to use a free microcontroller core on my Spartan 3 FPGA. There are quite some free cores available, b...
14 comments posted 20yrs
posted by idontwant
14 comments posted 20yrs posted by idontwant

DDR Termination

I am creating a design using a Xilinx Virtex II Pro and some DDR memory. downloaded the Xilinx ML361 DDR Ref design to...
1 comments posted 20yrs
posted by maxascent
1 comments posted 20yrs posted by maxascent

Compiler to FPSLIC

Hi everyone, I'm considering making a compiler for Atmels FPSLIC (combined microcontroller with FPGA). The idea is to m...
19 comments posted 20yrs
posted by usenet.s
19 comments posted 20yrs posted by usenet.s

Why does Synplify add clock buffers?

I have an Actel design with a 3 clocks. I need to define two of them in Synplify (v8.5): define_clock -name {n:clk2} -f...
4 comments posted 20yrs
posted by burn.sir
4 comments posted 20yrs posted by burn.sir

FPGA FAQ and the spam problem

Having seen way too much spam on this newsgroup lately, I have come with a possible solution that just might work. Add...
6 comments posted 20yrs
posted by burn.sir
6 comments posted 20yrs posted by burn.sir

Help needed

Hi, I have a IP block which is responsible of receiving all different kinds of external inputs and condition them. Once...
3 comments posted 20yrs
posted by fpgalearner
3 comments posted 20yrs posted by fpgalearner

who know what is the problem

who know what is the problem: those four error C:\copy_project\exemple6\top_ise>map processor_stub.ngd Release 8.1.03i...
2 comments posted 20yrs
posted by zhangxun0501
2 comments posted 20yrs posted by zhangxun0501

Infer dual-clock block RAM for Xilinx

Anyone has code templates for infering a dual-port, dual-clock, block RAM (RAMB16) for Xilinix using Synplicity and VHD...
7 comments posted 20yrs
posted by akhailtash
7 comments posted 20yrs posted by akhailtash

shared BRAM between PPC and FPGA fabric

Hi I am trying to implement a shared memory interface between PPC and FPGA fabric. I am using EDK to create a dual port...
2 comments posted 20yrs
posted by amitshukla1979
2 comments posted 20yrs posted by amitshukla1979

one question for a error of map

is anyone know what is means of this error please! thanks advance! C:\copy_project\exemple5\top_ise\toto2>map processor...
0 comments posted 20yrs
posted by zhangxun0501
0 comments posted 20yrs posted by zhangxun0501