Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Is there anything fundamentally wrong with this code?

entity my_entity is port ( clock : in std_logic; reset : in std_logic; input_signal : in std_logic; output_signal : out...
7 comments posted 20yrs
posted by simon.stockton
7 comments posted 20yrs posted by simon.stockton

incremental synthesis xst ise 8.1

We are working on a project with some vhdl entity re-instantiated several times. We would like to use incremental synth...
0 comments posted 20yrs
posted by marcobuffa
0 comments posted 20yrs posted by marcobuffa

Multiple Independent Circuits on a Single FPGA

Question: Is it possible / feasible / easy to implement a design on an FPGA such that two or more circuits are guarante...
13 comments posted 20yrs
posted by ajrae
13 comments posted 20yrs posted by ajrae

How is the max clock rate of a device fixed?

Hi, I'd like to know how a manufacturer arrives at the max clock rate of a particular speed grade of a device? For exam...
4 comments posted 20yrs
posted by reeves
4 comments posted 20yrs posted by reeves

Viterbi IP Core

Hello all, I am in lookout for a Viterbi IP Core for my project aimed for programming in Xilinx Virtex II Pro device. T...
0 comments posted 20yrs
posted by venkat.japan
0 comments posted 20yrs posted by venkat.japan

cannot be synthesized, bad synchronous description

In connection with "Create Timing Constraints" the error ERROR:Xst:827 occurs. We have the following fragment in our pr...
0 comments posted 20yrs
posted by ingenrespons
0 comments posted 20yrs posted by ingenrespons

driving high speed ADC using an FPGA

Hi Everyone, I am wondering if it would be possible to drive a 800 MHz 10 bit parellel A/D using an FPGA which has a 100...
4 comments posted 20yrs
posted by jayasanka.piyaratna
4 comments posted 20yrs posted by jayasanka.piyaratna

MaxPlus2 and the Byteblaster MV

For a legacy project I have MaxPlus2 with the Byteblaster MV. For a reason unknown to me, the Programmer modal tells me...
5 comments posted 20yrs
posted by none
5 comments posted 20yrs posted by none

RIO Reference clock oscillator part

In the RIO UG, two particular crystal oscillators parts are not just recommended but in effect mandated have to be used...
0 comments posted 20yrs
posted by spam
0 comments posted 20yrs posted by spam

FPGA availability & distribution options.

I read the thread on xilinx online shop issues. So how are the other options? (Altera, Lattice, Actel) - Priceing on sm...
3 comments posted 20yrs
posted by pbdelete
3 comments posted 20yrs posted by pbdelete

blowfish encryption algorithm

i m trying to implement blowfish encyption algorithm on spartan 3 board. so can any one tell me where i can find some he...
2 comments posted 20yrs
posted by chinmayshah.edi
2 comments posted 20yrs posted by chinmayshah.edi

FPGA + FTDI

Hello: Does anyone know if there is a simple PCB out there with a Xilinx FPGA (almost anything would work, Spartan III...
4 comments posted 20yrs
posted by emh203
4 comments posted 20yrs posted by emh203

FPGA + MAC board?

Is there any lowpriced board with _just_ a FPGA + ethernet 100 Mbps interface?
4 comments posted 20yrs
posted by pbdelete
4 comments posted 20yrs posted by pbdelete

Virtex 4 Unbonded IOB

Hi, I'm trying to use the unbonded IOB's available in the virtex 4 (lx25) as route through's to allow one input to fano...
0 comments posted 20yrs
posted by alastairlynch
0 comments posted 20yrs posted by alastairlynch