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How is the max clock rate of a device fixed?

Hi,

I'd like to know how a manufacturer arrives at the max clock rate of a particular speed grade of a device? For example, if we have the Xilinx Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit of 200 MHz fixed? If I build a design for which I make sure that all stages complete under, say 4ns, for the XC2VP50, I would benefit if I can clock the FPGA at 250 MHz. What issues would prevent a higher clock rate from being allowed?

Also, if it's based on various calculations, how do you end up with so round figures as 200 MHz or 400 MHz?

Thanks.

Reply to
Ken Reeves
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Just ignore that number of Fmax, if your timing simulation tells you that the clock period can be shorter. Watch the max output frequency of the DCM though. Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Reply to
Symon

There have to be some timing cathegories, thus the round numbers. Ever wondered why resistors are available in 1%, 5%, 10% margin, that is the same.

And while your board may only be used at lab conditions, the specified timing is met in the full temperature range, the full supply voltage range(s). Meaning, the specified timing is met at for the chip worst case.

Rene

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Reply to
Rene Tschaggelar

The DCM output is specified up to 450 MHz. The maximum PowerPC clock is 400 MHz. The "Toggle Frequency (for export control)" is 1050 MHz. Minimum clock period to meet address write cycle time is specified as 1.25 ns (800 MHz). Where do you find 200 MHz as a limit of this silicon from the data sheet?

Reply to
John_H

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