Hi all,
I was going through the datasheet of virtex2 , in which i read that
"each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable- bits of distributed SelectRAM memory, or a 16-bit variable-tap shift register element."
In the diagrams given in the viretx2 datasheet for cascadable shift register , i don't seen any clock at all.
Can anybody clarify on this implementation???
Regards, Prav
Prav,
It is common practice to draw simplified block diagrams without the clock connection when all components are clocked from the same source. The blocks shown in the Virtex 2 user guide are each SRLC16, which have a Q output for variable delay plus a Q15 output for cascading. When connecting in a long variable shifter design, normally the Q15 output is attached to the next SRLC16 and the Q outputs are multiplexed using the upper bits of the delay as the selector. Then the lower 4 bits of the desired delay can route to all SRLC16's in the chain.
Regards, Gabor
prav wrote:
See, specifically, Figure 21 on page 16 of "Module 2: Functional Description" (pdf page 24) from v3.4 of the "Virtex-II Complete Data Sheet (All four modules)"
Where the DI and WS are illustrated on the LUT with the write strobe generated as "WSG" from the Write Enable and Clock.
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