[cross-post] group on systemC language

Hi Al,

You can sign up on the main page,

Regards, Hans.

Hi Hans, In news.groups.questions HT-Lab wrote: []

thanks for the pointer. I actually knew about that forum, but I kind of dislike web-forums in general and I'd prefer to read and post articles through my newsreader rather than a clumsy web-interface.

I also do not like the idea to splitting communities and I may imagine the accellera forum would be the best choice indeed... Maybe I should try to look for an http-to-nntp bridge instead.

Al

I fully agree with you, unfortunately setting up say comp.lang.systemc is a lengthy process.

Having said that, the SystemC forums are actually quite good and this is all thanks to a handfull of experts who answers all questions.

Regards, Hans.

and I may imagine

Hi Hans, In comp.arch.fpga HT-Lab wrote: []

I think the process is not so long and I can even volunteer to write up an RFD but the real point is whether there will be enough traffic to justify a new group. I guess I'll need to show up on those forums first and get a feeling whether a group will be useful or not. I know of certain forums which map one to one newsgroup content in order to allow user to choose their favourite interface, without breaking the community, but this will require some efforts on the accellera side.

The added value of having a newsgroup is the possibility to cross-post efficiently especially when you want two languages to interact. I'm considering the possibility to have my model written in SystemC while the testbench written in vhdl, leveraging the benefits of the OSVVM library.

It might be that systemc forums are equally followed by lots of vhdl experts, but IMHO the possibility to merge the two world on usenet greatly improves the quality of the thread.

Al

That is unusual, I suspect you are better off using SCV as you might hit some mix language interface issues (records are not always straightforward on a SC/VHDL interface, use simple structs on SC only).

definitely, Alan Fitch is a language guru of both SystemC and VHDL and he answers a lot of questions on the forum.

but IMHO the possibility to merge the two world on usenet

Regards, Hans.

Hi Hans, In comp.arch.fpga HT-Lab wrote: []

There are two motivations behind this choice:

1. our system engineer is willing to dig into systemC for architecture exploration in the first place. We can profit of the model in order to build our verification environment *soon* in the project.
2. our fpga guys are not so much willing to spend time in learning systemC, while they could feel more confortable with the OSVVM since they know already the language.

The first point is a structural element that we are missing in our design flow. Too often the architecture is based on not so well founded choices and as the systems grow more complex, there's an increasing need to get the architecture right at the very beginning.

The second point is to enhance our current verification flow which is too often lagging behind. There's an unreasonable perception that going to the bench soon will reveal problems quicker. If we had a reference model and a verification environment early in the project I believe we can shift our mindset and spend less time in testing/debugging the hardware.