Latest threads in Field-Programmable Gate Arrays

detailed description on the archetecture of FPGA's/CPLD's

Hello, I am verry new to this Field and i would be verry happy if anybody would sujjest me a link or any document which...

3 20yrs

guruprasad

3 20yrs guruprasad

boundary scan through Virtex

hi all, I have a interface board developed and am trying to configure it but it give me error :565 saying error at bit...

0 20yrs

aborundiya

0 20yrs aborundiya

EDK and SYSGEN

Any buddy know how the following can be done. I need to connect the model developed in sysgen to EDK desgin. The EDK de...

3 20yrs

fpgalearner

3 20yrs fpgalearner

bizzare unexplained random errors w/ Lattice 4256V CPLD

We are using VHDL on a new design with a Lattice 4256V and are running into problems with our shift registers. We're us...

4 20yrs

shawnn

4 20yrs shawnn

Improvement suggestions for Xilinx ChipScope

Hi Xilin, As a first time user of Xilinx ChipScope, I have many feelings about its usage. 1. First of all, it is an exc...

2 20yrs

wtxwtx

2 20yrs wtxwtx

mux problem

hi, i want to write a verilog module for a 32 channel MUX with data width of 8. following is the module i wrote and it...

0 20yrs

manusha

0 20yrs manusha

ESL using Spartan 3/3E kits

Hi, I was wondering if it is possible to use the ESL approach for building applications on Spartan 3/3# starter kits? T...

0 20yrs

niravrraval

0 20yrs niravrraval

ESL and Spartan Starter Kit

Hi, Is it possible to do SystemC design using the Spartan 3/3E starter kits? I was wondering if the DK design suite and...

0 20yrs

niravraval

0 20yrs niravraval

windrvr for Linux broken in 2.6.16

The two versions of the Jungo windrvr drivers I was trying were: http://www.jungo.com/download/WD801LN.tgz and http://w...

4 20yrs

cole

4 20yrs cole

Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler

Hi group, Are there any problems with chaining multiple instances of the clock doubler from this link together?...

13 20yrs

doomeddave

13 20yrs doomeddave

Problem with DCM simulation models

Hi all, I have the following problem: I have a Virtex-4 Board (ML403). The Virtex-4 is ES. To use the DCM I have to add...

1 20yrs

taileb.mehdi

1 20yrs taileb.mehdi

Deadlock PLB

Hi, I need some direction and advice on integrating PLB slave. I have a design which i want to integrate with processor...

1 20yrs

fpgalearner

1 20yrs fpgalearner

RESET pin on NIOS II processor

Hi all, I have a problem driving the RESET pin on a NIOS II processor. I expect that when I pull LOW this pin, the NIOS...

1 20yrs

alessandro.strazzero

1 20yrs alessandro.strazzero

50-th Anniversary of the CORDIC Algorithm

50-th Anniversary of the CORDIC Algorithm Exactly 50 years ago - in the 1956 - the first Jack Volder's publication, des...

4 20yrs

vladimir

4 20yrs vladimir

BFM and ISE simulator

Can anybuddy tell me how can i make BFM work with ISE simulator or Active-HDL simulator. Actually these are the ONLY op...

1 20yrs

fpgalearner

1 20yrs fpgalearner

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays