Field-Programmable Gate Arrays

boundary scan through Virtex

hi all, I have a interface board developed and am trying to configure it but it give me error :565 saying error at bit...

0 comments posted 20yrs

posted by aborundiya

0 comments posted 20yrs posted by aborundiya

EDK and SYSGEN

Any buddy know how the following can be done. I need to connect the model developed in sysgen to EDK desgin. The EDK de...

3 comments posted 20yrs

posted by fpgalearner

3 comments posted 20yrs posted by fpgalearner

bizzare unexplained random errors w/ Lattice 4256V CPLD

We are using VHDL on a new design with a Lattice 4256V and are running into problems with our shift registers. We're us...

4 comments posted 20yrs

posted by shawnn

4 comments posted 20yrs posted by shawnn

Improvement suggestions for Xilinx ChipScope

Hi Xilin, As a first time user of Xilinx ChipScope, I have many feelings about its usage. 1. First of all, it is an exc...

2 comments posted 20yrs

posted by wtxwtx

2 comments posted 20yrs posted by wtxwtx

mux problem

hi, i want to write a verilog module for a 32 channel MUX with data width of 8. following is the module i wrote and it...

0 comments posted 20yrs

posted by manusha

0 comments posted 20yrs posted by manusha

ESL using Spartan 3/3E kits

Hi, I was wondering if it is possible to use the ESL approach for building applications on Spartan 3/3# starter kits? T...

0 comments posted 20yrs

posted by niravrraval

0 comments posted 20yrs posted by niravrraval

ESL and Spartan Starter Kit

Hi, Is it possible to do SystemC design using the Spartan 3/3E starter kits? I was wondering if the DK design suite and...

0 comments posted 20yrs

posted by niravraval

0 comments posted 20yrs posted by niravraval

windrvr for Linux broken in 2.6.16

The two versions of the Jungo windrvr drivers I was trying were: http://www.jungo.com/download/WD801LN.tgz and http://w...

4 comments posted 20yrs

posted by cole

4 comments posted 20yrs posted by cole

Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler

Hi group, Are there any problems with chaining multiple instances of the clock doubler from this link together?...

13 comments posted 20yrs

posted by doomeddave

13 comments posted 20yrs posted by doomeddave

Problem with DCM simulation models

Hi all, I have the following problem: I have a Virtex-4 Board (ML403). The Virtex-4 is ES. To use the DCM I have to add...

1 comments posted 20yrs

posted by taileb.mehdi

1 comments posted 20yrs posted by taileb.mehdi

Deadlock PLB

Hi, I need some direction and advice on integrating PLB slave. I have a design which i want to integrate with processor...

1 comments posted 20yrs

posted by fpgalearner

1 comments posted 20yrs posted by fpgalearner

RESET pin on NIOS II processor

Hi all, I have a problem driving the RESET pin on a NIOS II processor. I expect that when I pull LOW this pin, the NIOS...

1 comments posted 20yrs

posted by alessandro.strazzero

1 comments posted 20yrs posted by alessandro.strazzero

50-th Anniversary of the CORDIC Algorithm

50-th Anniversary of the CORDIC Algorithm Exactly 50 years ago - in the 1956 - the first Jack Volder's publication, des...

4 comments posted 20yrs

posted by vladimir

4 comments posted 20yrs posted by vladimir

BFM and ISE simulator

Can anybuddy tell me how can i make BFM work with ISE simulator or Active-HDL simulator. Actually these are the ONLY op...

1 comments posted 20yrs

posted by fpgalearner

1 comments posted 20yrs posted by fpgalearner

quartus 5.1 assignment_defaults.qdf

Hello, While I'd swear I had this working at one point, two of us are finding that Quartus 5.1 (under Linux) is ignorin...

0 comments posted 20yrs

posted by brehob

0 comments posted 20yrs posted by brehob